VERIFICATION AND VALIDATION

[Abbs]

Hi.

This group is of real help to people that really need help and
assistance during the course of designing and programning. Well, all
these while i was into desiging and development. now i have been
shifted to VERIFICATION and TESTING in VHDL. i have done verification
earlier in TESTBENCHES, wrote a code and given input vectors and
verified the output vectors. Is this basically how testing is done, or
lots more into it. I'am just aware of this way of testing of the VHDL
code in TESTBENCHES.
If there are many other ways of testing and validation which i'am
unaware of PLEASE let me know.


I'am refering a book:

Writing Testbenches: Functional Verification of HDL Models, Second
Edition
by Janick Bergeron.


well its just the begening.
Can i please be informed of sites or pdf doc that will help me gain
more knowledge in this.

Along with this i request to get info, ideas on the
importance,advantages, of testing, diffrent tools used in verification.

One last doubt, in verification, do we even work on STATIC TIME
ANALYSIS and SYNTHESIS.
or this is done by the designer itself..

would be very thankful to get replies soon.

Cheers

Bye

 

Several comments:
1. You will find several verification answers and a good place to post
interesting verification questions at
http://verificationguild.com/ under MAIN
2. In my books I have encouraged the use of transaction-based
verification, which can be done in VHDL. I dislike the use of
waveform stimulus files as a means to define directed tests. But ...
3. The languages and technology has matured since the days of VHDL'93,
and I now definitely prefer SystemVerilog with assertions as a means to
verify designs. SystemVerilog provides the facilities to build a
testbench that is transaction-based with constraints and can be
coverage-driven. You can also top that with VMM (Verification
Methodology Manual for SystemVerilog by Janick) to facilitate the
design of the testbench environment. In any case, SystemVerilog can
be used in mixed-mode with VHDL, along with assertions written in SVA (
SystemVerilog assertions) or PSL,
If I have a choice today to pick a language for verification, I would
definitely pick SystemVerilog over VDHL. Of course, the tradeoff here
is the cost of learning SV and tool cost if you do not have access to a
SV simulator.
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Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
http://www.abv-sva.org/ ben@abv-sva.org
* Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
* Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
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