VERIFICATION AND TESTPLAN

[Abbs]

hi masters.
this faq is very helpful. i need help!!!
i'am currently doing verification of the zdut made in VHDL. i need to
prepare testplan before i start. so if i get an idea how to make a
testplan would be very helpfull.
for example. i need to test a FIFO. this is just to make me understand.
but i have to verify more complex designs. so if any one out here, can
help me with this, keeping an FIFO as an example would be very
greatfull.
thanks
Abbs...

 

[apurv]

Hi Abbs,

Look at this link
http://www.us.design-reuse.com/showArticle.jhtml;jsessionid=S3LWWHLBYNJD2QSNDBGCKH0CJUMEKJVN?articleID=22104451

That will help you to understand VE plan and testplan

Thanks
apurv

Abbs wrote:

hi masters.
this faq is very helpful. i need help!!!
i'am currently doing verification of the zdut made in VHDL. i need to
prepare testplan before i start. so if i get an idea how to make a
testplan would be very helpfull.
for example. i need to test a FIFO. this is just to make me understand.
but i have to verify more complex designs. so if any one out here, can
help me with this, keeping an FIFO as an example would be very
greatfull.
thanks
Abbs...

 

[Abbs]

hiii Apurv..

Look at this link
http://www.us.design-reuse.com/showArticle.jhtml;jsessionid=S3LWWHLBYNJD2QSNDBGCKH0CJUMEKJVN?articleID=22104451

this link directed me to a site, which said:

We're sorry. The page that was requested does not exist.
Please hit the back button on your browser to return to the last page
you visited. Or explore any of our sections via the links to the left.
Thank you for visiting D&R Web Site.

guess its expired. im trying to get info on how efficiently
verification can be done, for which a testplan should be developed.
based on it, i can look forward and use the same technique.

Thanks for all your support