O
Oliver
Guest
Hi!
I have a problem with my Verifault-XL fault simulation.
I wrote a Stimulus file called test.verifault.
When I compile this Stimulus file with my Virtuoso Schematic Composer
Analysis Environment for Verilog-XL I get for every Verifault
command the following error message:
Warning! Skipping foreign VERIFAULT-XL task $fs_ .......
(I'm using IC5 Cadence)
Could anybody help me please?
Thanks in advance!!!
Oliver
I have a problem with my Verifault-XL fault simulation.
I wrote a Stimulus file called test.verifault.
When I compile this Stimulus file with my Virtuoso Schematic Composer
Analysis Environment for Verilog-XL I get for every Verifault
command the following error message:
Warning! Skipping foreign VERIFAULT-XL task $fs_ .......
(I'm using IC5 Cadence)
Could anybody help me please?
Thanks in advance!!!
Oliver