vector truncation rules

[nemgreen@yahoo.co.uk]

I've been looking to find the rules for an assign where the RHS is
wider than the LHS.
I've found examples of the simple case where vectors with identical
base index (eg 0) are assigned, but I'm not sure about the following:

assign target_vec[7:3] = source_vec[24:8];

Which bits of source_vec get assigned to which bits of target_vec?

Can anyone enlighten me?

Thanks

 

[Jonathan Bromley]

On Fri, 13 Jul 2007 11:33:42 -0700, "nemgreen@yahoo.co.uk"
<nemgreen@yahoo.co.uk> wrote:

;

Which bits of source_vec get assigned to which bits of target_vec?

The less significant bits:

source 24..13,12..8
target 7..3

Surplus MSBs [24:13] are silently thrown away.

Synthesis tools will probably warn you about the mismatch
whenever they can, because it suggests that you may have
misunderstood the hardware. Simulators most certainly will
not, because the truncation is the expected behaviour.

Copying a narrow source into a wide target is a little
trickier, partly because there may (in some situations)
be sign extension, and partly because the way in which
the source expression is evaluated can be affected by
the width of the target. These issues have been discussed
here many times before, but if you ask questions about
specific situations you are likely to get helpful answers.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[nemgreen@yahoo.co.uk]

On 13 Jul, 20:34, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Fri, 13 Jul 2007 11:33:42 -0700, "nemgr...@yahoo.co.uk"

nemgr...@yahoo.co.uk> wrote:
assign target_vec[7:3] = source_vec[24:8];

Which bits of source_vec get assigned to which bits of target_vec?

The less significant bits:

source 24..13,12..8
target 7..3

Surplus MSBs [24:13] are silently thrown away.

Synthesis tools will probably warn you about the mismatch
whenever they can, because it suggests that you may have
misunderstood the hardware. Simulators most certainly will
not, because the truncation is the expected behaviour.

Copying a narrow source into a wide target is a little
trickier, partly because there may (in some situations)
be sign extension, and partly because the way in which
the source expression is evaluated can be affected by
the width of the target. These issues have been discussed
here many times before, but if you ask questions about
specific situations you are likely to get helpful answers.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Thanks Jonathan

You've helped me better understand someone else's code

 

[glen herrmannsfeldt]

Jonathan Bromley wrote:

On Fri, 13 Jul 2007 11:33:42 -0700, "nemgreen@yahoo.co.uk"
nemgreen@yahoo.co.uk> wrote:

assign target_vec[7:3] = source_vec[24:8];

Which bits of source_vec get assigned to which bits of target_vec?

The less significant bits:
(snip)

are silently thrown away.

Synthesis tools will probably warn you about the mismatch
whenever they can, because it suggests that you may have
misunderstood the hardware. Simulators most certainly will
not, because the truncation is the expected behaviour.

In some cases, the synthesizer doesn't quite follow the
verilog rules. One is:

assign target=source+1;

or, more likely

assign target=source+1'b1;

Where, if I remember right, when target and source have the same
width the sum is also supposed to have that width, but many synthesis
tools will generate the sum with one more bit, and then complain.

Copying a narrow source into a wide target is a little
trickier, partly because there may (in some situations)
be sign extension, and partly because the way in which
the source expression is evaluated can be affected by
the width of the target. These issues have been discussed
here many times before, but if you ask questions about
specific situations you are likely to get helpful answers.

I believe one must treat separately the case where the
destination width is known (as above) and when it is not:

assign target={one+1'b1,two-1'b1};

-- glen

 

[parag_paul@hotmail.com]

module top;
reg [1:7]a= 'd112;
reg [1:4]out ;

initial
begin
#1 out = a[1:7];
#1 $display( out);
end

endmodule


Just an example. YES VCS truncates to the lower most guys

See the output

0


-Parag