vector assignment in VHDL

[Vadim Rusu]

Hi,

I am trying to have a std_logic_vector which I want to define based on a
variable. In other words, say I have the vector V(31 downto 0) and I
only use RAM_SIZE bits. The rest of the vector I want to assign to 0. Is
there any way I can do this? So instead of having

V(31-RAM_SIZE downto 0)= "0000000000000"

I want something more elegant, like:

V(31-RAM_SIZE downto 0) = (32-RAM_SIZE) "0"

Is this doable in vhdl?


Thanks,
Vadim

 

[Symon]

V(31-RAM_SIZE downto 0) <= (others => '0');
Syms.