Vector assignment in Verilog?

[Shenli]

Hi all,

Is there Vector assignment in Verilog like C show below:
reg [31:0] vectors [2:0] = {5, 6, 7};
Or I have to assign vectors one by one?

Best regards,
Davy

 

[dbwalker0min@gmail.com]

Davy,

In standard verilog, you definitely have to define a memory one-by-one
(although you could read them from a file with $readmemx). In
SystemVerilog, you're supposed to be able to do this. From the
SystemVerilog LRM...

--------------
2.7 Array literals
Array literals are syntactically similar to C initializers, but with
the replicate operator ( {{}} ) allowed.

int n[1:2][1:3] = {{0,1,2},{3{4}}};

The nesting of braces must follow the number of dimensions, unlike in
C. However, replicate operators can be
nested. The inner pair of braces in a replication is removed. A
replication expression only operates within one
dimension.

int n[1:2][1:3] = {2{{3{4, 5}}}}; // same as
{{4,5,4,5,4,5},{4,5,4,5,4,5}}

If the type is not given by the context, it must be specified with a
cast.

typedef int triple [1:3];
$mydisplay(triple'{0,1,2});

Array literals can also use their index or type as a key, and a default
key value (see Section 7.13).

b = {1:1, default:0}; // indexes 2 and 3 assigned 0

---------

Unfortunately, this does not seem to work in ncverilog. So the short
answer is you have to assign vectors one-by-one in ncsim (as far as I
know).

David Walker

On Jan 24, 6:10 pm, "Shenli" <zhushe...@gmail.com> wrote:

Hi all,

Is there Vector assignment in Verilog like C show below:
reg [31:0] vectors [2:0] = {5, 6, 7};
Or I have to assign vectors one by one?

Best regards,
Davy

 

dbwalker0min@gmail.com wrote:

In
SystemVerilog, you're supposed to be able to do this. From the
SystemVerilog LRM...

--------------
2.7 Array literals
Array literals are syntactically similar to C initializers, but with
the replicate operator ( {{}} ) allowed.

int n[1:2][1:3] = {{0,1,2},{3{4}}};
....
If the type is not given by the context, it must be specified with a
cast.

typedef int triple [1:3];
$mydisplay(triple'{0,1,2});

David, you are quoting the old Accellera LRM here. Due
to problems with ambiguity between this syntax and
Verilog concatenations, this syntax was changed in the
IEEE SystemVerilog standard.

You can use the "cast" syntax to specify the type. If you
want to get the type from context (which is only legal in
so-called assignment-like contexts), you can leave out
the type, but you must still specify the ' before the curly
brace. The "cast" is no longer an actual cast, but is part
of the syntax of the literal.

So the correct syntax is now '{1,2,3}. This has also been
renamed an "assignment pattern". The IEEE standard
also generalizes it in a number of ways, making it more
flexible.

Unfortunately, this does not seem to work in ncverilog. So the short
answer is you have to assign vectors one-by-one in ncsim (as far as I
know).

NC-Verilog supports basic assignment patterns, with
the syntax standardized by the IEEE.

 

[dbwalker0min@gmail.com]

How about that! Maybe it means I have to shell out the $$ for an IEEE
LRM.

David Walker

On Jan 25, 12:35 pm, s...@cadence.com wrote:

dbwalker0...@gmail.com wrote:
In
SystemVerilog, you're supposed to be able to do this. From the
SystemVerilog LRM...

--------------
2.7 Array literals
Array literals are syntactically similar to C initializers, but with
the replicate operator ( {{}} ) allowed.

int n[1:2][1:3] = {{0,1,2},{3{4}}};
...
If the type is not given by the context, it must be specified with a
cast.

typedef int triple [1:3];
$mydisplay(triple'{0,1,2});David, you are quoting the old Accellera LRM here. Due
to problems with ambiguity between this syntax and
Verilog concatenations, this syntax was changed in the
IEEE SystemVerilog standard.

You can use the "cast" syntax to specify the type. If you
want to get the type from context (which is only legal in
so-called assignment-like contexts), you can leave out
the type, but you must still specify the ' before the curly
brace. The "cast" is no longer an actual cast, but is part
of the syntax of the literal.

So the correct syntax is now '{1,2,3}. This has also been
renamed an "assignment pattern". The IEEE standard
also generalizes it in a number of ways, making it more
flexible.

Unfortunately, this does not seem to work in ncverilog. So the short
answer is you have to assign vectors one-by-one in ncsim (as far as I
know).NC-Verilog supports basic assignment patterns, with
the syntax standardized by the IEEE.