VDHL Mealy sequence detector

hello, i need help with VHDL sequence detector (101) project. I wrote VHDL file but output dout goes to 1 when machine is on "Next state" and not on "Present state". In other words machine gives output 1 on the falling edge of clock and not rising edge. anyone can help me? thanks
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity riconoscitoremealy is
Port ( clk : in STD_LOGIC;
din : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end riconoscitoremealy;
architecture Behavioral of riconoscitoremealy is
type state is (st0, st1, st2);
signal present_state, next_state : state;
begin
syncronous_process : process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
present_state <= st0;
else
present_state <= next_state;
end if;
end if;
end process;
next_state_and_output_decoder : process(present_state, din)
begin
dout <= '0';
case (present_state) is
when st0 =>
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st0;
dout <= '0';
end if;
when St1 =>
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st2;
dout <= '0';
end if;
when St2 =>
if (din = '1') then
next_state <= st1;
dout <= '1';
else
next_state <= st0;
dout <= '0';
end if;
when others =>
next_state <= st0;
dout <= '0';
end case;
end process;
end Behavioral;

 

[rickman]

gameover.xboxservice@gmail.com wrote on 9/1/2017 4:43 PM:
> hello, i need help with VHDL sequence detector (101) project. I wrote VHDL file but output dout goes to 1 when machine is on "Next state" and not on "Present state". In other words machine gives output 1 on the falling edge of clock and not rising edge. anyone can help me? thanks

Your code is very hard to read because it lacks any formatting, but it looks
basically ok. You assign present_state in a clocks process and assign the
next state and output in a combinatorial process. In a simulation this will
give the appearance of everything changing on the rising edge of the clock.
present_state will be updated to the existing value of next_state,
next_state will receive a new value and dout will receive a new value.

I don't see anything that should be updated on the falling edge of clk.

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

 

On Saturday, September 2, 2017 at 8:43:14 AM UTC+12, gameover.x...@gmail.com wrote:
> hello, i need help with VHDL sequence detector (101) project. I wrote VHDL file but output dout goes to 1 when machine is on "Next state" and not on "Present state". In other words machine gives output 1 on the falling edge of clock and not rising edge. anyone can help me? thanks

A Mealy machine output can depend on both state and input. You could note that dout assigned to '1' is dependent on din. The solution to your issue might be as simple as assigning values of din on the same rising edge of clk.

 

[Charles Bailey]

On 2017-09-01 15:43, gameover.xboxservice@gmail.com wrote:

hello, i need help with VHDL sequence detector (101) project. I wrote VHDL file but output dout goes to 1 when machine is on "Next state" and not on "Present state". In other words machine gives output 1 on the falling edge of clock and not rising edge. anyone can help me? thanks
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity riconoscitoremealy is
Port ( clk : in STD_LOGIC;
din : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end riconoscitoremealy;
architecture Behavioral of riconoscitoremealy is
type state is (st0, st1, st2);
signal present_state, next_state : state;
begin
syncronous_process : process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
present_state <= st0;
else
present_state <= next_state;
end if;
end if;
end process;
next_state_and_output_decoder : process(present_state, din)
begin
dout <= '0';
case (present_state) is
when st0 =
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st0;
dout <= '0';
end if;
when St1 =
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st2;
dout <= '0';
end if;
when St2 =
if (din = '1') then
next_state <= st1;
dout <= '1';
else
next_state <= st0;
dout <= '0';
end if;
when others =
next_state <= st0;
dout <= '0';
end case;
end process;
end Behavioral;

The way your next_state_and_output_decoder process is coded, dout is set
to a '1' what present_state=st2 and din='1' and is '0' otherwise.

If fact, if you wanted to, you could pull all the logic for dout out of
the next_state_and_output_decoder process and code it in a separate
statement like this:
dout <= din when present_state=st2 else '0';
and you would get equivalent behavior.

If it appears that dout is going active on the falling edge of clk it is
probably because din is changing on the falling edge of clk.

Also, the "others" clause in your case statement is unreachable because
present_state can have only 3 values and those are already covered in
the case statement.

Charles Bailey