D
da
Guest
Hi,
Does anyone know how to specify a technology library when simulating a
mapped verilog netlist using vcs. I mapped an rtl level verilog design
using design compiler and have the library in .db format only. Now vcs
cant find definitions of modules in the netlist.
thanx
Does anyone know how to specify a technology library when simulating a
mapped verilog netlist using vcs. I mapped an rtl level verilog design
using design compiler and have the library in .db format only. Now vcs
cant find definitions of modules in the netlist.
thanx