D
da
Guest
Hi,
Does anyone know how to specify the technology library when trying to
simulate a synthesized verilog netlist using vcs. I just have the
library in .db format and i mapped the rtl design using design
compiler.
thanx
Does anyone know how to specify the technology library when trying to
simulate a synthesized verilog netlist using vcs. I just have the
library in .db format and i mapped the rtl design using design
compiler.
thanx