vcs simulation for memory

[Diandian Zhang]

Hi, I am new to Verilog. Can anyone tell me, how can I simulate a
Memory (eg. reg[15:0] A[15:0]) using vcs? I can only view the waves of
the registers. Thanks a lot.

Diandian

 

[Andy Peters]

zhangdidi@hotmail.com (Diandian Zhang) wrote in message news:<7d12548d.0310221255.6b05f134@posting.google.com>...

Hi, I am new to Verilog. Can anyone tell me, how can I simulate a
Memory (eg. reg[15:0] A[15:0]) using vcs? I can only view the waves of
the registers. Thanks a lot.

You probably have to write the code that reads from and writes to your memory.

--a

 

[ABW]

"Diandian Zhang" <zhangdidi@hotmail.com> wrote in message
news:7d12548d.0310221255.6b05f134@posting.google.com...

Hi, I am new to Verilog. Can anyone tell me, how can I simulate a
Memory (eg. reg[15:0] A[15:0]) using vcs? I can only view the waves of
the registers. Thanks a lot.

If your design simulates but you can't put memory A into waveform the

problem may be a lack of compilation/simulation switch. Note that mere
potential of observing register/signal on waveform eats resources and since
memories are rather big some simulators require you to explicitely allow
memories to be observable on waveform (even in full debug mode). If you
don't provide appropriate switch they assume that you don't want to watch
memory. This assumption allows them to simulate faster.
Maybe this is the problem (it is also possible that VCS does not allow you
to trace memories). Read VCS documentation on switches.

 

[Chris Briggs]

My understanding is that the waves file format doesn't support
recording information about memories. I've used VCD, VCD+ and SST and
all of these have this limitation. I understand that some 3rd-party
wave viewers have their own proprietary formats that will store memory
values in waves. I believe (but don't quote me) that Debussy from
Novas and also Undertow from Veritools can do this, but you'll have to
check for yourself.

You can also define some wires that point to the memory locations
you're interested in and these wires will get captured in waves. I
wouldn't do this for large memories though. E.g.,

reg [15:0] A[15:0]

wire [15:0] A0 = A[0];
wire [15:0] A1 = A[1];
wire [15:0] A2 = A[2];
etc.

-cb

 

[Srinivasan Venkataramanan]

Hi,
VCS used to have an inbuilt-PLI called $vcdplusmemorydump which can dump
the entire memory snapshot to be viewed inside VirSim viewer. I don't use
VCS any more so can't comment on its usage/updates etc.

HTH,
Srinivasan

--
Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

http://www.noveldv.com http://www.deeps.org
I don't speak for Intel