VCS- How to use libraries

[Anil Dalwani]

Hi,

I was wondering if there is any option to include libraries in vhdl
design while elaboration with vcs (libraries compiled from vhdl code,
and libraries are being in vhdl design - I am using scs command for
elaboration) ?

The problem is that if I use the "use" clause in my vhdl file , it is
giving no problem and getting the instance. If I don't have the "use"
clause in my design then the tool is not scanning the libraries for
the components and giving warnings in the elaboration that this
component is not found because it is unbound.

Is there any option that I need to give on command line with
elaboration command ?

Appreciate any help..
Regards,
-Anil

 

[Just an Illusion]

Hi Anil

Anil Dalwani wrote:

Hi,

I was wondering if there is any option to include libraries in vhdl
design while elaboration with vcs (libraries compiled from vhdl code,
and libraries are being in vhdl design - I am using scs command for
elaboration) ?

The problem is that if I use the "use" clause in my vhdl file , it is
giving no problem and getting the instance. If I don't have the "use"
clause in my design then the tool is not scanning the libraries for
the components and giving warnings in the elaboration that this
component is not found because it is unbound.


This is the requirement demand by the IEEE 1076.

If you want that your component are instantiate as black box, you can
directly define their prototype into the architecture_declarative_part,
and don't use any 'use'

Is there any option that I need to give on command line with
elaboration command ?


If you have compile all your components architecture (before) into work

library, that is not necessary, because work is implicitly used.

Appreciate any help..
Regards,
-Anil

JaI