VCS compile Error

[Venkia]

I am using mixed hdl option -mhdl and +vhdllib<lib name> options in VCS
simulator..I am getting an error " DONT KNOW HOW TO MAKE TARGET
libvhdl_object.o Make exited with status 1" please help me in solving
this

 

[gorjusborg]

You may want to try a VHDL newsgroup.
This group is focused on Verilog.

Venkia wrote:

I am using mixed hdl option -mhdl and +vhdllib<lib name> options in VCS
simulator..I am getting an error " DONT KNOW HOW TO MAKE TARGET
libvhdl_object.o Make exited with status 1" please help me in solving
this

 

[Ajeetha]

Hi,
2 suggestions:

1. Contact sim_support@synopsys.com
2. Send me a small enoguh example, I may be able to try and get it
resolved.

Regards
Ajeetha, CVC

Venkia wrote:

I am using mixed hdl option -mhdl and +vhdllib<lib name> options in VCS
simulator..I am getting an error " DONT KNOW HOW TO MAKE TARGET
libvhdl_object.o Make exited with status 1" please help me in solving
this

 

[Petter Gustad]

"Venkia" <venkatakris@yahoo.com> writes:

I am using mixed hdl option -mhdl and +vhdllib<lib name> options in VCS
simulator..I am getting an error " DONT KNOW HOW TO MAKE TARGET
libvhdl_object.o Make exited with status 1" please help me in solving
this

Sounds like something got corrupted and make is confused. Try to (do a
backup first) remove the csrc and simv.daidir directories and the
simv executable and then rerun the vcs command to build them over
again.

Petter
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