VCD format with Modelsim

Hi,

I'm trying to generate a vcd file from a 2 VHDL systems, one simulated
with ModelSim and another with NCSim and compare the results from both.

Unfortunately, the VCD file generated by ModelSim is spliting the
signals into bits, while NCSim keeps the buses.
Does anyone know which switch or command use to keep the signals with
their original width in Modelsim? Or the other way around. How to split
into bits the NCSim signals automatically to write to the VCD file?

Thanks.

 

[Mike Treseler]

loli_pardo@hotmail.com wrote:

I'm trying to generate a vcd file from a 2 VHDL systems, one simulated
with ModelSim and another with NCSim and compare the results from both.

Unfortunately, the VCD file generated by ModelSim is spliting the
signals into bits, while NCSim keeps the buses.

I would make the verification part of the vhdl testbench.
If both simulators find the same expected values,
I don't have to worry about waveform display file formats.

-- Mike Treseler

 

[Kim Enkovaara]

loli_pardo@hotmail.com wrote:

I'm trying to generate a vcd file from a 2 VHDL systems, one simulated
with ModelSim and another with NCSim and compare the results from both.

Unfortunately, the VCD file generated by ModelSim is spliting the
signals into bits, while NCSim keeps the buses.

Have you tried to convert the NCsim vcd to wlf (vcd2wlf utility that comes
with Modelsim). Then just use the waveform compare function inside
Modelsim.

--Kim

 

My idea was to work with NCsim rather than ModelSim, because of license
limitations with ModelSim. Do you know if it's possible to write the
VCD file in ModelSim keeping the bus format?

Thanks,

Loli.