vcd file genarating problem

[narasimha k]

i am using icaura verilog, problem :is vcd file is not genarating these are my design and testbench please any one explain thi
s
my design is
====================================
module fulladder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
reg sum,carry;
always@(*)
begin
sum = a^b^c;
carry = (a&b)|(b&c)|(c&a);
end
endmodule
========================================

and my test bench is
---------------------------------------
module fulladder_tb;
reg a,b,c;
wire sum,carry;
fulladder DUT(a,b,c,sum,carry);
initial
begin
a=0;b=0;c=0;
#10;
a=0;b=0;c=1;
#10;
a=0;b=1;c=0;
#10;
a=0;b=1;c=1;
#10;
a=1;b=0;c=0;
#10;
a=1;b=0;c=1;
#10;
a=1;b=1;c=0;
#10;
a=1;b=1;c=1;
#10;
end
initial begin

$display("+++++++++++++++++++++++++++++++++++++++++");
$display("------FULL-ADDER TRUTH TABLE-------------");
$display("+++++++++++++++++++++++++++++++++++++++++");
$display(" A B C SUM CARRY");
$monitor(" %b %b %b %b %b",a,b,c,sum,carry);
end
initial begin
$dumpfile ("fulladde.vcd");
$dumpvars (0, fulladde);
#50;
$finish;
end

endmodule

 

[Cary R.]

On 6/15/2013 11:22 PM, narasimha k wrote:

i am using icaura verilog, problem :is vcd file is not genarating
these are my design and testbench please any one explain this

Did Icarus report a problem during the compilation phase? The version I
have would not compile the code you posted and pointed to the problem in
the $dumpvars() statement. Specifically the second argument is not
defined. The second and any subsequent arguments to $dumpvars() are
variables or scopes to dump to the VCD file. I'm assuming you intended
to use fulladder_tb instead of fulladde.

With this change and extending the time after the $dumpvars to #80
results in no compilation errors and when run the full table and a valid
VCD file are generated.

Cary