A
ALuPin
Guest
Hi everybody,
I have an warning message that no output is dependant on the input 'In_sel'.
Why is 'Out_data' not dependent on l_transmit (which is dependent on
var_transmit (which is dependent on In_sel) ) ?
(I use QuartusII software)
Thank you for your help.
Here is the shortened code:
-------------------------------------
-------------------------------------
entity xy is
port( In_sel : in std_logic;
...
Out_data : out std_logic;
);
end xy;
architecture yz of xy is
signal l_data : std_logic;
signal l_transmit : std_logic;
begin
Out_data <= l_data;
process(Reset, Clk)
variable var_transmit : std_logic;
begin
if Reset='1' then
l_transmit <= '0';
l_data <= '0';
elsif rising_edge(Clk) then
l_data <= l_data;
l_transmit <= l_transmit;
var_transmit := l_transmit;
...
if In_sel='1' then
var_transmit:= '1';
end if;
if var_transmit='1' then
l_data <= '1';
end if;
l_transmit <= var_transmit;
end if;
end process;
end yz;
I have an warning message that no output is dependant on the input 'In_sel'.
Why is 'Out_data' not dependent on l_transmit (which is dependent on
var_transmit (which is dependent on In_sel) ) ?
(I use QuartusII software)
Thank you for your help.
Here is the shortened code:
-------------------------------------
-------------------------------------
entity xy is
port( In_sel : in std_logic;
...
Out_data : out std_logic;
);
end xy;
architecture yz of xy is
signal l_data : std_logic;
signal l_transmit : std_logic;
begin
Out_data <= l_data;
process(Reset, Clk)
variable var_transmit : std_logic;
begin
if Reset='1' then
l_transmit <= '0';
l_data <= '0';
elsif rising_edge(Clk) then
l_data <= l_data;
l_transmit <= l_transmit;
var_transmit := l_transmit;
...
if In_sel='1' then
var_transmit:= '1';
end if;
if var_transmit='1' then
l_data <= '1';
end if;
l_transmit <= var_transmit;
end if;
end process;
end yz;