Variables, signals: behavioral and post-route simulation

I'm learning the diff between variables and signals,
and I've found this site:
http://esd.cs.ucr.edu/labs/tutorial/sig_var.vhd
with a corresponding picture here:
http://esd.cs.ucr.edu/labs/tutorial/sig_var.jpg

I've changed the source file to this

library ieee;
use ieee.std_logic_1164.all;

entity sig_var is port (
d1, d2, d3 : in std_logic;
res1, res2, res3 : out std_logic);
end sig_var;

architecture behv of sig_var is
signal sig_s1: std_logic;
signal sig_s2: std_logic;

begin

proc1: process(d1,d2,d3)
variable var_s1: std_logic;

begin
var_s1 := d1 and d2;
res1 <= var_s1 xor d3;
end process;

proc2: process (d1,d2,d3)
begin
sig_s1 <= d1 and d2;
res2 <= sig_s1 xor d3;
end process;

sig_s2 <= d1 and d2;
res3 <= sig_s2 xor d3;

end behv;


and this are the simulation results:
http://img521.imageshack.us/img521/346/simulations.gif

As you can see, behavioral and post-route don't match.
Is there something wrong with the VHD source,
or I just don't get the idea behind behavioral simulation?

Post route works as I have expected.

(I've started this thread as a variable/signal issue,
but it turned into behavioral/post-route simulation.)

 

[Alan Fitch]

On 01/06/12 08:53, aleksazr@gmail.com wrote:

I'm learning the diff between variables and signals,
and I've found this site:
http://esd.cs.ucr.edu/labs/tutorial/sig_var.vhd
with a corresponding picture here:
http://esd.cs.ucr.edu/labs/tutorial/sig_var.jpg

I've changed the source file to this

library ieee;
use ieee.std_logic_1164.all;

entity sig_var is port (
d1, d2, d3 : in std_logic;
res1, res2, res3 : out std_logic);
end sig_var;

architecture behv of sig_var is
signal sig_s1: std_logic;
signal sig_s2: std_logic;

begin

proc1: process(d1,d2,d3)
variable var_s1: std_logic;

begin
var_s1 := d1 and d2;
res1 <= var_s1 xor d3;
end process;

proc2: process (d1,d2,d3)
begin
sig_s1 <= d1 and d2;
res2 <= sig_s1 xor d3;
end process;

sig_s2 <= d1 and d2;
res3 <= sig_s2 xor d3;

end behv;


and this are the simulation results:
http://img521.imageshack.us/img521/346/simulations.gif

As you can see, behavioral and post-route don't match.
Is there something wrong with the VHD source,
or I just don't get the idea behind behavioral simulation?

There's an error in your proc2 - sig_s1 should be in the sensitivity list,

regards
Alan

Post route works as I have expected.

(I've started this thread as a variable/signal issue,
but it turned into behavioral/post-route simulation.)

--
Alan Fitch

 

[Alan Fitch]

On 01/06/12 15:02, aleksazr@gmail.com wrote:

On Friday, June 1, 2012 11:07:44 AM UTC+2, Alan Fitch wrote:
On 01/06/12 08:53, aleksazr@gmail.com wrote:
I'm learning the diff between variables and signals,
and I've found this site:
http://esd.cs.ucr.edu/labs/tutorial/sig_var.vhd
with a corresponding picture here:
http://esd.cs.ucr.edu/labs/tutorial/sig_var.jpg

I've changed the source file to this
snip

As you can see, behavioral and post-route don't match.
Is there something wrong with the VHD source,
or I just don't get the idea behind behavioral simulation?

There's an error in your proc2 - sig_s1 should be in the sensitivity list,

regards
Alan


Post route works as I have expected.

(I've started this thread as a variable/signal issue,
but it turned into behavioral/post-route simulation.)


--
Alan Fitch

Yes, that fixed it. Now both simulations show the same.
Too bad ISE doesn't support the ALL keyword.
(sig_s1 is missing in the original file as well,
and ISE didn't warn me about it)

Thanks

Yes, it's interesting that Isim (the Xilinx Simulator) seems to have
some VHDL 2008 support. It'll be interesting to see what the language
support for synthesis is like in Vivado,

Alan

--
Alan Fitch

 

On Friday, June 1, 2012 11:07:44 AM UTC+2, Alan Fitch wrote:

On 01/06/12 08:53, aleksazr@gmail.com wrote:
I'm learning the diff between variables and signals,
and I've found this site:
http://esd.cs.ucr.edu/labs/tutorial/sig_var.vhd
with a corresponding picture here:
http://esd.cs.ucr.edu/labs/tutorial/sig_var.jpg

I've changed the source file to this

library ieee;
use ieee.std_logic_1164.all;

entity sig_var is port (
d1, d2, d3 : in std_logic;
res1, res2, res3 : out std_logic);
end sig_var;

architecture behv of sig_var is
signal sig_s1: std_logic;
signal sig_s2: std_logic;

begin

proc1: process(d1,d2,d3)
variable var_s1: std_logic;

begin
var_s1 := d1 and d2;
res1 <= var_s1 xor d3;
end process;

proc2: process (d1,d2,d3)
begin
sig_s1 <= d1 and d2;
res2 <= sig_s1 xor d3;
end process;

sig_s2 <= d1 and d2;
res3 <= sig_s2 xor d3;

end behv;


and this are the simulation results:
http://img521.imageshack.us/img521/346/simulations.gif

As you can see, behavioral and post-route don't match.
Is there something wrong with the VHD source,
or I just don't get the idea behind behavioral simulation?

There's an error in your proc2 - sig_s1 should be in the sensitivity list,

regards
Alan


Post route works as I have expected.

(I've started this thread as a variable/signal issue,
but it turned into behavioral/post-route simulation.)


--
Alan Fitch

Yes, that fixed it. Now both simulations show the same.
Too bad ISE doesn't support the ALL keyword.
(sig_s1 is missing in the original file as well,
and ISE didn't warn me about it)

Thanks