variables and max frequences

[zlotawy]

Hello,
Device: vp30-5ff1152

In my project there is a state machine. The machine suppose to be in the
last state as long as the user defines in constants. At least that's what I
figured. Is there any other way than using variable and counting cycles of
the clock?

The moment when machines leaves the last state depends on function IF which
explores several conditions each time. Those are mathematical conditions
such as: if variable_counter modulo 7 equls 0 then sth, otherwise if
variable_counter minus 1 modulo 5 equls 0 then sth and so on...

Thanks to that Maximum Frequency decreases a lot. "Optimizing unit" lasts
very long.

The notation
variable_counter:=variable_counter+1
has a very bad influance.

With that notation: Max freq 133.672MHz
Without that notation: Max freq 30 MHz

My idea is not to use the variables but to solve the problem in a differant
way.


What does that notation mean: "Found area constraint ratio of 100 (+ 5) on
block"?

Somebody told me to use Constraint Times, but I have no clue how to do that.
I appreciate any advice.

Best regards,
Wojtek

 

[Mike Treseler]

zlotawy wrote:

In my project there is a state machine. The machine suppose to be in the
last state as long as the user defines in constants. At least that's what I
figured. Is there any other way than using variable and counting cycles of
the clock?

Not really. If I have to wait, I either count or
watch for a handshake input.

With that notation: Max freq 133.672MHz
Without that notation: Max freq 30 MHz

My idea is not to use the variables but to solve the problem in a differant
way.

Variables aren't the problem.
Doing everything at one state might be.
Try adding states and spreading out the work.

-- Mike Treseler

 

[KJ]

"zlotawy" <spawnek@wp.NO_SPAM.pl> wrote in message
news:feqpkd$1tq$1@inews.gazeta.pl...

Hello,
Device: vp30-5ff1152

In my project there is a state machine. The machine suppose to be in the
last state as long as the user defines in constants.
Not sure what that is supposed to mean.

At least that's what I figured. Is there any other way than using variable
and counting cycles of the clock?

State machines are a means to accomplishing a goal. If the goal is to count

clocks then do that. If the goal is to do something when some input signal
changes then do that.

The moment when machines leaves the last state depends on function IF
which explores several conditions each time. Those are mathematical
conditions such as: if variable_counter modulo 7 equls 0 then sth,
otherwise if variable_counter minus 1 modulo 5 equls 0 then sth and so
on...

Thanks to that Maximum Frequency decreases a lot. "Optimizing unit" lasts
very long.

Most likely having to do with the modulo operator. When you compute 'x

modulo 7' or 'x modulo 5' those computations are likely going to be very
time consuming if written as you've done. The ones that come for free are
'x modulo 4', 'x modulo 8', (i.e. something modulo 2^n) since those simply
involve masking off the least significant few bits. While straight division
is synthesizable, it is generally a long combinatorial path to compute.

The notation
variable_counter:=variable_counter+1
has a very bad influance.

Your performance has nothing do with the counter, or the use of variables.

With that notation: Max freq 133.672MHz
Without that notation: Max freq 30 MHz

My idea is not to use the variables but to solve the problem in a
differant way.

I'd suggest looking at how to better compute 'modulo 7' and 'modulo 5' in a

faster manner. I'd suggest looking into 'lpm_divide', the remainder will be
the modulo, that can then be fed into your state machine. Lpm_divide (and
other synchronous dividers) typically take several clock cycles to perform
the math but they can be run at a very high clock rate.

KJ

 

[psihodelia@googlemail.com]

Is there any other way than using variable and counting cycles of the clock?
Yes. Bit shifting is very robust operation. If your maximum in counter

is supposed to be small, you can use a shift register, shifting 'Hi'
on each clock. The highest bit in this shift register will indicate
maximum.

Psiho

 

[Andy]

On Oct 14, 6:46 am, "psihode...@googlemail.com"
<psihode...@googlemail.com> wrote:

Is there any other way than using variable and counting cycles of the clock?

Yes. Bit shifting is very robust operation. If your maximum in counter
is supposed to be small, you can use a shift register, shifting 'Hi'
on each clock. The highest bit in this shift register will indicate
maximum.

Psiho

I have also seen some tools support wait statements (on clocks) inside
loops, but that is by no means standardized across synthesis tools.

I also agree with the others: variables are not the problem unless you
are trying to do too much in one clock cycle. If so, it is simple
enough to rearrange the reads relative to the writes of the variables
to divide the operations up among multiple clock cycles.

Also, the modulo operations with non-power-of-two operands is very
time and resource consuming. Is the count small enough that you could
use a look up table stored in RAM to accomplish it?

Andy