N
Nicolas Matringe
Guest
Hello all
I was wondering if it was possible (read synthesizable) to assign a
variable to a signal in a clocked process *outside* the reset/clock
edge condition.
My basic idea is to use a variable instead of an intermediate signal.
Here is what I have in mind (basic "heartbeat" led)
process (clk, rst) is
variable cntr : natural range 0 to DIV - 1;
variable led : std_ulogic;
begin -- process
if rst = '1' then
cntr <= 0;
led := '0';
elsif rising_edge(clk) then
if clk_en = '1' then
if cntr = 0 then
cntr <= DIV - 1;
led := not led;
else
cntr := cntr - 1;
end if;
end if;
end if;
htbt_led <= led; -- <- is this OK?
end process;
Nicolas
I was wondering if it was possible (read synthesizable) to assign a
variable to a signal in a clocked process *outside* the reset/clock
edge condition.
My basic idea is to use a variable instead of an intermediate signal.
Here is what I have in mind (basic "heartbeat" led)
process (clk, rst) is
variable cntr : natural range 0 to DIV - 1;
variable led : std_ulogic;
begin -- process
if rst = '1' then
cntr <= 0;
led := '0';
elsif rising_edge(clk) then
if clk_en = '1' then
if cntr = 0 then
cntr <= DIV - 1;
led := not led;
else
cntr := cntr - 1;
end if;
end if;
end if;
htbt_led <= led; -- <- is this OK?
end process;
Nicolas