variable scope

[Marco]

Hi,
if I define a variable or something else (like an array of bit I may
use as flags) in the architecture section of an entity, the top one in
my project, will this variable be visible for all the other components
I recall within that same architecture section?
Thanks,
Marco

 

[Mike Treseler]

Marco wrote:

if I define a variable or something else (like an array of bit I may
use as flags) in the architecture section of an entity, the top one in
my project, will this variable be visible for all the other components
I recall within that same architecture section?

No, because a variable must be declared in a process.
However, using a single process architecture you
can cover the full scope with a variable.
For an example, see the reference design here:

http://home.comcast.net/~mike_treseler/


-- Mike Treseler

 

[Marco]

Mike,
thanks for the likěnk to your code, very interesting.
I'll make some test and I'll be back with other questions.
Marco

 

[Marco]

Hi,
I decided to place all the signals (as variables are only for
processes) I want to be visible from each entity and I put them into a
package, should this work?
Thanks,
Marco

 

[Mike Treseler]

Marco wrote:

Hi,
I decided to place all the signals (as variables are only for
processes) I want to be visible from each entity and I put them into a
package, should this work?

No. For synthesis, your choices are 1. multiple
processes using common architecture signals
or 2.procedures using common variables in
a single process (as in my reference design).

-- Mike Treseler

 

[Marco]

Are these the only ways to share signals/variables?
I'd like to explain you something more on my project: my FPGA gets
commands (like "read inputs" or "write outputs") from a serial
communication with a DSP. It has more than just some I/Os, it has an
SPI temp-sensor to handle, a quadrature decoder and something else. I
was planning to create an entity for each feature (GPIO,
temp-sensor...) and let these entities be controlled by another
TOP-entity called control-unit, which has to take care about the
communication (commands to read and answers to send) and job
assignments to each block. To do this I tought to use a status register
and some other signals to be accessible be every entity inside my
project. As example: control_units sets a GPIO read flag, the GPIO
reads and builds up a vector with the answer, when ready it then sets
another flag, say GPIO_answer_ready and the control_unit send back the
proper answer to the DSP.
Thanks,
Marco

 

[Andy]

Plain vanilla variables (not SHARED variables so declared, which aren't
synthesizable anyway), are limited in scope to the process in which
they are declared, and any procedures/functions also declared within
that process.

Signals can be declared in packages (so-called global signals), but
most synthesis tools treat them as separate local signals wherever they
are referenced (bad idea IMHO), if they accept them at all.

So your choices are, declare the status register as a signal in a high
level architecture, and pass it down through the ports to lower level
architectures.

Or, like Mike suggests, use a single architecture, with single process
and create your hierarchy with functions/procedures defined within that
process (or within other functions/procedures). Trying to implement
hierachy this way can get messy if you need more than two levels (i.e.
the process and the functions/procedures declared within it).

Andy

 

[Mike Treseler]

Andy wrote:

So your choices are, declare the status register as a signal in a high
level architecture, and pass it down through the ports to lower level
architectures.

Yes. Note that my reference design only uses 50 of
the many thousands of logic cells available in most
devices. At about this size, I have a reusable entity
that needs a testbench.

At the device level I use a two-level hierarchy
of single process entities.

top
local bus signals and instances only -- no processes
instance of entity 1, mapped to local bus and or top ports
instance of entity 2, mapped to local bus and or top ports
instance of entity 3, mapped to local bus and or top ports
instance of entity 4, mapped to local bus and or top ports
end entity top

http://groups.google.com/groups/search?q=treseler+%22two-level%22

-- Mike Treseler