Variable or signal?

[Xin Xiao]

I'm modeling a cache memory in vhdl. What would be the difference between
using a variable or a signal to model my memory?

type mem_cache is array (range) of lines;

signal cache : mem_cache;

- or -

variable cache : mem_cache;

 

[KJ]

"Xin Xiao" <x@x.com> wrote in message
news:fkms97$caq$1@nsnmrro2-gest.nuria.telefonica-data.net...

I'm modeling a cache memory in vhdl. What would be the difference between
using a variable or a signal to model my memory?

type mem_cache is array (range) of lines;

signal cache : mem_cache;

- or -

variable cache : mem_cache;

Functionally there would be no difference at all, if you can write a model
using signals, you can write it using variables.

Using variables runs somewhat faster than using signals because there is
more overhead for the simulator with signals than with variables. Try
writing it both ways and see for yourself. It's not a huge difference
though.

KJ

 

[Xin Xiao]

tank you

"KJ" <kkjennings@sbcglobal.net> wrote in message
news:ZPCbj.85008$YL5.47432@newssvr29.news.prodigy.net...

"Xin Xiao" <x@x.com> wrote in message
news:fkms97$caq$1@nsnmrro2-gest.nuria.telefonica-data.net...
I'm modeling a cache memory in vhdl. What would be the difference between
using a variable or a signal to model my memory?

type mem_cache is array (range) of lines;

signal cache : mem_cache;

- or -

variable cache : mem_cache;

Functionally there would be no difference at all, if you can write a model
using signals, you can write it using variables.

Using variables runs somewhat faster than using signals because there is
more overhead for the simulator with signals than with variables. Try
writing it both ways and see for yourself. It's not a huge difference
though.

KJ