Variable Optimized Away

C

Calvin Ball

Guest
Hello,
I am having a problem where Xilinx ISE is trimming away a variable
that I need, tempShifts. I can still implement the module but I am not
sure what it is doing with my variable. This says to me that
tempShifts isn't being trimmed... Explanations?

Also this module uses the shift and add 3 algorithm to convert binary
to BCD format. Specifically this converts a 16 bit binary number into
5 BCD digits.

module binaryBCD(
input [15:0] binaryIn, //input 16bit number
output reg [19:0] bcdOut //5 display BCD output
);

reg [35:0] tempShifts; //temporary storage while computing

always @(binaryIn)
begin
tempShifts = 0;
//the method used is shift and add 3
//this requires 16 total shifts, first three are done here
tempShifts[18:3] = binaryIn;

repeat(13)
begin //for the method if any BCD digit is over 4 add three then
shift
if (tempShifts[19:16] > 4)
tempShifts[19:16] = tempShifts[19:16] + 3;
if (tempShifts[23:20] > 4)
tempShifts[23:20] = tempShifts[23:20]+ 3;
if (tempShifts[27:24] > 4)
tempShifts[27:24] = tempShifts[27:24] + 3;
if (tempShifts[31:28] > 4)
tempShifts[31:28] = tempShifts[31:28] + 3;
if (tempShifts[35:32] > 4)
tempShifts[35:32] = tempShifts[35:32] + 3;

tempShifts = tempShifts << 1;
end
//save the final output
bcdOut = tempShifts[35:16];
end
endmodule

The warning I get is below:
WARNING:Xst:646 - Signal <tempShifts> is assigned but never used. This
unconnected signal will be trimmed during the optimization process.
 
Calvin Ball wrote:
Hello,
I am having a problem where Xilinx ISE is trimming away a variable
that I need, tempShifts. I can still implement the module but I am not
sure what it is doing with my variable. This says to me that
tempShifts isn't being trimmed... Explanations?

Also this module uses the shift and add 3 algorithm to convert binary
to BCD format. Specifically this converts a 16 bit binary number into
5 BCD digits.

module binaryBCD(
input [15:0] binaryIn, //input 16bit number
output reg [19:0] bcdOut //5 display BCD output
);

reg [35:0] tempShifts; //temporary storage while computing

always @(binaryIn)
begin
tempShifts = 0;
//the method used is shift and add 3
//this requires 16 total shifts, first three are done here
tempShifts[18:3] = binaryIn;

repeat(13)
begin //for the method if any BCD digit is over 4 add three then
shift
if (tempShifts[19:16] > 4)
tempShifts[19:16] = tempShifts[19:16] + 3;
if (tempShifts[23:20] > 4)
tempShifts[23:20] = tempShifts[23:20]+ 3;
if (tempShifts[27:24] > 4)
tempShifts[27:24] = tempShifts[27:24] + 3;
if (tempShifts[31:28] > 4)
tempShifts[31:28] = tempShifts[31:28] + 3;
if (tempShifts[35:32] > 4)
tempShifts[35:32] = tempShifts[35:32] + 3;

tempShifts = tempShifts << 1;
end
//save the final output
bcdOut = tempShifts[35:16];
end
endmodule

The warning I get is below:
WARNING:Xst:646 - Signal <tempShifts> is assigned but never used. This
unconnected signal will be trimmed during the optimization process.
Click to expand...
XST has a brain-dead way of giving warnings about intermediate results.
Basically the only bits of tempShifts that are used are effectively
renamed to bcdOut. By the way I was under the impression that the
repeat operator was not synthesizable. Does this code actually work
in the hardware?

-- Gabor
 
On Jun 9, 2:34 pm, Gabor <ga...@szakacs.invalid> wrote:
Calvin Ball wrote:
Hello,
I am having a problem where Xilinx ISE is trimming away a variable
that I need, tempShifts. I can still implement the module but I am not
sure what it is doing with my variable. This says to me that
tempShifts isn't being trimmed... Explanations?

Also this module uses the shift and add 3 algorithm to convert binary
to BCD format. Specifically this converts a 16 bit binary number into
5 BCD digits.

module binaryBCD(
   input [15:0] binaryIn,          //input 16bit number
   output reg [19:0] bcdOut        //5 display BCD output
   );

   reg [35:0] tempShifts;  //temporary storage while computing

   always @(binaryIn)
           begin
                   tempShifts = 0;
                   //the method used is shift and add 3
                   //this requires 16 total shifts, first three are done here
                   tempShifts[18:3] = binaryIn;

                   repeat(13)
                   begin   //for the method if any BCD digit is over 4 add three then
shift
                           if (tempShifts[19:16] > 4)
                                   tempShifts[19:16] = tempShifts[19:16] + 3;
                           if (tempShifts[23:20] > 4)
                                   tempShifts[23:20] = tempShifts[23:20]+ 3;
                           if (tempShifts[27:24] > 4)
                                   tempShifts[27:24] = tempShifts[27:24] + 3;
                           if (tempShifts[31:28] > 4)
                                   tempShifts[31:28] = tempShifts[31:28] + 3;
                           if (tempShifts[35:32] > 4)
                                   tempShifts[35:32] = tempShifts[35:32] + 3;

                           tempShifts = tempShifts << 1;
                   end
                   //save the final output
                   bcdOut = tempShifts[35:16];
           end
endmodule

The warning I get is below:
WARNING:Xst:646 - Signal <tempShifts> is assigned but never used. This
unconnected signal will be trimmed during the optimization process.

XST has a brain-dead way of giving warnings about intermediate results.
Basically the only bits of tempShifts that are used are effectively
renamed to bcdOut.  By the way I was under the impression that the
repeat operator was not synthesizable.  Does this code actually work
in the hardware?

-- Gabor
Click to expand...
Yea I have successfully implemented this code on a Nexys 2 development
board, XCS3500E FPGA.
 
On Jun 9, 3:16 pm, Calvin Ball <ballcal...@gmail.com> wrote:
On Jun 9, 2:34 pm, Gabor <ga...@szakacs.invalid> wrote:









Calvin Ball wrote:
Hello,
I am having a problem where Xilinx ISE is trimming away a variable
that I need, tempShifts. I can still implement the module but I am not
sure what it is doing with my variable. This says to me that
tempShifts isn't being trimmed... Explanations?

Also this module uses the shift and add 3 algorithm to convert binary
to BCD format. Specifically this converts a 16 bit binary number into
5 BCD digits.

module binaryBCD(
   input [15:0] binaryIn,          //input 16bit number
   output reg [19:0] bcdOut        //5 display BCD output
   );

   reg [35:0] tempShifts;  //temporary storage while computing

   always @(binaryIn)
           begin
                   tempShifts = 0;
                   //the method used is shift and add 3
                   //this requires 16 total shifts, first three are done here
                   tempShifts[18:3] = binaryIn;

                   repeat(13)
                   begin   //for the method if any BCD digit is over 4 add three then
shift
                           if (tempShifts[19:16] > 4)
                                   tempShifts[19:16] = tempShifts[19:16] + 3;
                           if (tempShifts[23:20] > 4)
                                   tempShifts[23:20] = tempShifts[23:20]+ 3;
                           if (tempShifts[27:24] > 4)
                                   tempShifts[27:24] = tempShifts[27:24] + 3;
                           if (tempShifts[31:28] > 4)
                                   tempShifts[31:28] = tempShifts[31:28] + 3;
                           if (tempShifts[35:32] > 4)
                                   tempShifts[35:32] = tempShifts[35:32] + 3;

                           tempShifts = tempShifts << 1;
                   end
                   //save the final output
                   bcdOut = tempShifts[35:16];
           end
endmodule

The warning I get is below:
WARNING:Xst:646 - Signal <tempShifts> is assigned but never used. This
unconnected signal will be trimmed during the optimization process.

XST has a brain-dead way of giving warnings about intermediate results.
Basically the only bits of tempShifts that are used are effectively
renamed to bcdOut.  By the way I was under the impression that the
repeat operator was not synthesizable.  Does this code actually work
in the hardware?

-- Gabor

Yea I have successfully implemented this code on a Nexys 2 development
board, XCS3500E FPGA.
Click to expand...
To implement this wouldn't it just copy the structure as many times as
needed, in this case 13 times?
 
On 06/10/2011 12:19 AM, Calvin Ball wrote:
On Jun 9, 3:16 pm, Calvin Ball<ballcal...@gmail.com> wrote:
On Jun 9, 2:34 pm, Gabor<ga...@szakacs.invalid> wrote:









Calvin Ball wrote:
Hello,
I am having a problem where Xilinx ISE is trimming away a variable
that I need, tempShifts. I can still implement the module but I am not
sure what it is doing with my variable. This says to me that
tempShifts isn't being trimmed... Explanations?

Also this module uses the shift and add 3 algorithm to convert binary
to BCD format. Specifically this converts a 16 bit binary number into
5 BCD digits.

module binaryBCD(
input [15:0] binaryIn, //input 16bit number
output reg [19:0] bcdOut //5 display BCD output
);

reg [35:0] tempShifts; //temporary storage while computing

always @(binaryIn)
begin
tempShifts = 0;
//the method used is shift and add 3
//this requires 16 total shifts, first three are done here
tempShifts[18:3] = binaryIn;

repeat(13)
begin //for the method if any BCD digit is over 4 add three then
shift
if (tempShifts[19:16]> 4)
tempShifts[19:16] = tempShifts[19:16] + 3;
if (tempShifts[23:20]> 4)
tempShifts[23:20] = tempShifts[23:20]+ 3;
if (tempShifts[27:24]> 4)
tempShifts[27:24] = tempShifts[27:24] + 3;
if (tempShifts[31:28]> 4)
tempShifts[31:28] = tempShifts[31:28] + 3;
if (tempShifts[35:32]> 4)
tempShifts[35:32] = tempShifts[35:32] + 3;

tempShifts = tempShifts<< 1;
end
//save the final output
bcdOut = tempShifts[35:16];
end
endmodule

The warning I get is below:
WARNING:Xst:646 - Signal<tempShifts> is assigned but never used. This
unconnected signal will be trimmed during the optimization process.

XST has a brain-dead way of giving warnings about intermediate results.
Basically the only bits of tempShifts that are used are effectively
renamed to bcdOut. By the way I was under the impression that the
repeat operator was not synthesizable. Does this code actually work
in the hardware?

-- Gabor

Yea I have successfully implemented this code on a Nexys 2 development
board, XCS3500E FPGA.

To implement this wouldn't it just copy the structure as many times as
needed, in this case 13 times?
Click to expand...
Doesn't this take an awful amount of logic resources ? If this is for a
display, or other human interface, there's generally no requirement to
update it faster than people can read. In that case, a version with a
state machine that requires N clocks would probably work just as well,
and be much more compact.
 
Calvin Ball wrote:
On Jun 9, 3:16 pm, Calvin Ball <ballcal...@gmail.com> wrote:
On Jun 9, 2:34 pm, Gabor <ga...@szakacs.invalid> wrote:









Calvin Ball wrote:
Hello,
I am having a problem where Xilinx ISE is trimming away a variable
that I need, tempShifts. I can still implement the module but I am not
sure what it is doing with my variable. This says to me that
tempShifts isn't being trimmed... Explanations?
Also this module uses the shift and add 3 algorithm to convert binary
to BCD format. Specifically this converts a 16 bit binary number into
5 BCD digits.
module binaryBCD(
input [15:0] binaryIn, //input 16bit number
output reg [19:0] bcdOut //5 display BCD output
);
reg [35:0] tempShifts; //temporary storage while computing
always @(binaryIn)
begin
tempShifts = 0;
//the method used is shift and add 3
//this requires 16 total shifts, first three are done here
tempShifts[18:3] = binaryIn;
repeat(13)
begin //for the method if any BCD digit is over 4 add three then
shift
if (tempShifts[19:16] > 4)
tempShifts[19:16] = tempShifts[19:16] + 3;
if (tempShifts[23:20] > 4)
tempShifts[23:20] = tempShifts[23:20]+ 3;
if (tempShifts[27:24] > 4)
tempShifts[27:24] = tempShifts[27:24] + 3;
if (tempShifts[31:28] > 4)
tempShifts[31:28] = tempShifts[31:28] + 3;
if (tempShifts[35:32] > 4)
tempShifts[35:32] = tempShifts[35:32] + 3;
tempShifts = tempShifts << 1;
end
//save the final output
bcdOut = tempShifts[35:16];
end
endmodule
The warning I get is below:
WARNING:Xst:646 - Signal <tempShifts> is assigned but never used. This
unconnected signal will be trimmed during the optimization process.
XST has a brain-dead way of giving warnings about intermediate results.
Basically the only bits of tempShifts that are used are effectively
renamed to bcdOut. By the way I was under the impression that the
repeat operator was not synthesizable. Does this code actually work
in the hardware?
-- Gabor
Yea I have successfully implemented this code on a Nexys 2 development
board, XCS3500E FPGA.

To implement this wouldn't it just copy the structure as many times as
needed, in this case 13 times?
Click to expand...
I presume it should be the same as: for (i = 0;i < 13; i = i + 1)
However in the past I have never tried "repeat" other than in test
benches. My "Verilog Golden Reference Guide" has this to say about
repeat for synthesis:

"Only synthesizable with some tools, and only then if the loop is
'broken' by a clock event..."

Apparently tools have advanced a bit since this book was written.

-- Gabor
 
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