Variable Frequency and Voltage Supply

[GaRY]

Hi,

I am very new in using FPGA. I wanna know is there any design of
information in FPGA use variable clock and variable voltage, coz I
want to find ways to reduce power when using FPGA.
Thx for the help.

GaRY

 

[Peter Alfke]

The supply voltage (except for I/Os) is dictated by the manufacturere,
so you have only a few percent to play with.
Dynamic power consumption is proportional to clock rate, so you have
enormous leeway, but watch out for min frequency limits on PLL and
DLL/DCM-controlled clocks.
Leakage current used to be insignificant, then became a few mA, and can
now be hundreds of mA. But it is inherently proportional to thechip
size, and worst for the newest FPGAs. (CoolRunner CPLDs are still unbeatable)

Peter Alfke
===============
GaRY wrote:

Hi,

I am very new in using FPGA. I wanna know is there any design of
information in FPGA use variable clock and variable voltage, coz I
want to find ways to reduce power when using FPGA.
Thx for the help.

GaRY

 

[GaRY]

Peter,

Thanks for your answer

GaRY