variable bus

[smily]

I have a variable bus and only want to give the input [`BITS-1:0] to to the
output [`BITS-1:0] for TEST

'include "../defines.v" // `define BITS = 8(but variable)

module bus_var1 (in, out );

input [`BITS-1:0] in;
output [`BITS-1:0] out;

electrical [`BITS-1:0] in;
electrical [`BITS-1:0] out;
integer i;

parameter real tdel = 3u from [0:inf);
parameter real trise = 1u from (0:inf);
parameter real tfall = 1u from (0:inf);

analog begin // count from 0 to `BITS
for (i=0; i<`BITS; i=i+1) begin

V(out) <+ transition(in, tdel,trise,tfall);
end
end
endmodule


Is there a possibility?

V(out) <+ V(in) // like in VHDL?

Regards smily

 

[Steven Sharp]

"smily" <smily1111@gmx.de> wrote in message news:<bd5a948e070158c7e306235f2ac3d5f7@localhost.talkaboutprogramming.com>...

to to the
output [`BITS-1:0] for TEST

I'm sorry, but I don't understand what you are trying to do.

Also, your testcase appears to be Verilog-AMS, not Verilog, so you may
have trouble getting advice here.