S
siso
Guest
A simple question about the keyword ' var ' in SystemVerilog. I'm not
sure I understand its significance reading the standard. Esspecially
when it is used in the port lists.
How this relates to the synthesys? Is it a strictly test bench thing
or can be used in the RTL as well?
I'll appreciate your help.
s1s0
sure I understand its significance reading the standard. Esspecially
when it is used in the port lists.
How this relates to the synthesys? Is it a strictly test bench thing
or can be used in the RTL as well?
I'll appreciate your help.
s1s0