Values larger than 32 bit using conv_std_logic_vector

  • Thread starter Willem Oosthuizen
  • Start date
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Willem Oosthuizen

Guest
signal D is defined as std_logic_vector(51 downto 0)

D <= conv_std_logic_vector(2**n+16#ff#,D'length); only works correctly for
integer n < 31. How can I make it work for integer n < 52 ?

Any suggestions? Why is there this 32 bit limit?
 
"Jon" <jon8spam@yahoo.com> wrote in message
news:d68b01eb.0307010716.6dccb209@posting.google.com...
"Willem Oosthuizen" <willy@asic.co.za> wrote in message
news:<bdrp4d$i48$1@ctb-nnrp2.saix.net>...
signal D is defined as std_logic_vector(51 downto 0)

D <= conv_std_logic_vector(2**n+16#ff#,D'length); only
works correctly for
integer n < 31. How can I make it work for integer n
52 ?

Any suggestions? Why is there this 32 bit limit?

Hi Willem,
VHDL defined the minimum supported range of an integer
to be -2^32
to (2^31)-1. Some simulators extended the range for
integers and you
would have to check to see if yours did.
One way not very efficient is to break up the number
into a sum of
integers each no greater than 2^32.

jon
Click to expand...
I know this is very pedantic :) but the range is guaranteed
to be
(-2^32)+1 to (2^31)-1, i.e. the most negative number is not
guaranteed by
the standard to be included. Of course in practice is always
is!

Regarding the original question, you might be able to
achieve something
similar using shifts. It's not clear from your original code
if n is a
constant or a signal. I shall assume it's a signal.

process(n)
begin
D <= (others => '0'); -- all bits 0
D(n) <= '1'); -- e.g. n = 0 => set bit 0, n = 1 =>
set bit 1
D(7 downto 0) <= X"FF";
end process;

If n is locally static (i.e. a constant), then you *should*
be able to write

D <= (n=> '1', 7 downto 0 => '1', others => '0');


kind regards

Alan

--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification *
Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood,
Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views
which are not the
views of Doulos Ltd., unless specifically stated.
 
On 1 Jul 2003 08:16:13 -0700, jon8spam@yahoo.com (Jon) wrote:

"Willem Oosthuizen" <willy@asic.co.za> wrote in message news:<bdrp4d$i48$1@ctb-nnrp2.saix.net>...
signal D is defined as std_logic_vector(51 downto 0)

D <= conv_std_logic_vector(2**n+16#ff#,D'length); only works correctly for
integer n < 31. How can I make it work for integer n < 52 ?

Any suggestions? Why is there this 32 bit limit?

Hi Willem,
VHDL defined the minimum supported range of an integer to be -2^32
to (2^31)-1.
Click to expand...
Minor correction: the minimum supported range of an integer is
-((2^32)-1) to +((2^32)-1)

Amost all tools do extend the lower range to -(2^32) though.

Regards,
Allan.
 
I said:
D <= conv_std_logic_vector(2**n+16#ff#,D'length);

Alan Said:
process(n)
begin
D <= (others => '0'); -- all bits 0
D(n) <= '1'); -- e.g. n = 0 => set bit 0, n = 1 =
set bit 1
D(7 downto 0) <= X"FF";
end process;
Click to expand...
This is not equivalent. What about the carry when n < 8 ?

"Alan Fitch" <alan.fitch@doulos.com> wrote in message
news:bdu5fd$6h4$1$8302bc10@news.demon.co.uk...
"Jon" <jon8spam@yahoo.com> wrote in message
news:d68b01eb.0307010716.6dccb209@posting.google.com...
"Willem Oosthuizen" <willy@asic.co.za> wrote in message
news:<bdrp4d$i48$1@ctb-nnrp2.saix.net>...
signal D is defined as std_logic_vector(51 downto 0)

D <= conv_std_logic_vector(2**n+16#ff#,D'length); only
works correctly for
integer n < 31. How can I make it work for integer n
52 ?

Any suggestions? Why is there this 32 bit limit?

Hi Willem,
VHDL defined the minimum supported range of an integer
to be -2^32
to (2^31)-1. Some simulators extended the range for
integers and you
would have to check to see if yours did.
One way not very efficient is to break up the number
into a sum of
integers each no greater than 2^32.

jon

I know this is very pedantic :) but the range is guaranteed
to be
(-2^32)+1 to (2^31)-1, i.e. the most negative number is not
guaranteed by
the standard to be included. Of course in practice is always
is!

Regarding the original question, you might be able to
achieve something
similar using shifts. It's not clear from your original code
if n is a
constant or a signal. I shall assume it's a signal.

process(n)
begin
D <= (others => '0'); -- all bits 0
D(n) <= '1'); -- e.g. n = 0 => set bit 0, n = 1 =
set bit 1
D(7 downto 0) <= X"FF";
end process;

If n is locally static (i.e. a constant), then you *should*
be able to write

D <= (n=> '1', 7 downto 0 => '1', others => '0');


kind regards

Alan

--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification *
Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood,
Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views
which are not the
views of Doulos Ltd., unless specifically stated.
Click to expand...
 
Hi Willem,
All you have to do is what Alan said execpt add 255 to D in places
of directly assigning the lsbs to 255. Using the right packages you
can do 2's complement signed or unsigned using std_logic_vector.

jon


"Willem Oosthuizen" <willy@asic.co.za> wrote in message news:<bdudo2$bda$1@ctb-nnrp2.saix.net>...
I said:
D <= conv_std_logic_vector(2**n+16#ff#,D'length);

Alan Said:
process(n)
begin
D <= (others => '0'); -- all bits 0
D(n) <= '1'); -- e.g. n = 0 => set bit 0, n = 1 =
set bit 1
D(7 downto 0) <= X"FF";
end process;

This is not equivalent. What about the carry when n < 8 ?

"Alan Fitch" <alan.fitch@doulos.com> wrote in message
news:bdu5fd$6h4$1$8302bc10@news.demon.co.uk...

"Jon" <jon8spam@yahoo.com> wrote in message
news:d68b01eb.0307010716.6dccb209@posting.google.com...
"Willem Oosthuizen" <willy@asic.co.za> wrote in message
news:<bdrp4d$i48$1@ctb-nnrp2.saix.net>...
signal D is defined as std_logic_vector(51 downto 0)

D <= conv_std_logic_vector(2**n+16#ff#,D'length); only
works correctly for
integer n < 31. How can I make it work for integer n
52 ?

Any suggestions? Why is there this 32 bit limit?

Hi Willem,
VHDL defined the minimum supported range of an integer
to be -2^32
to (2^31)-1. Some simulators extended the range for
integers and you
would have to check to see if yours did.
One way not very efficient is to break up the number
into a sum of
integers each no greater than 2^32.

jon

I know this is very pedantic :) but the range is guaranteed
to be
(-2^32)+1 to (2^31)-1, i.e. the most negative number is not
guaranteed by
the standard to be included. Of course in practice is always
is!

Regarding the original question, you might be able to
achieve something
similar using shifts. It's not clear from your original code
if n is a
constant or a signal. I shall assume it's a signal.

process(n)
begin
D <= (others => '0'); -- all bits 0
D(n) <= '1'); -- e.g. n = 0 => set bit 0, n = 1 =
set bit 1
D(7 downto 0) <= X"FF";
end process;

If n is locally static (i.e. a constant), then you *should*
be able to write

D <= (n=> '1', 7 downto 0 => '1', others => '0');


kind regards

Alan

--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification *
Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood,
Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views
which are not the
views of Doulos Ltd., unless specifically stated.
Click to expand...
 
"Jon" <jon8spam@yahoo.com> wrote in message
news:d68b01eb.0307022116.1e6d88a3@posting.google.com...
Hi Willem,
All you have to do is what Alan said execpt add 255 to D
in places
of directly assigning the lsbs to 255. Using the right
packages you
can do 2's complement signed or unsigned using
std_logic_vector.

jon


"Willem Oosthuizen" <willy@asic.co.za> wrote in message
news:<bdudo2$bda$1@ctb-nnrp2.saix.net>...
I said:
D <= conv_std_logic_vector(2**n+16#ff#,D'length);

Alan Said:
process(n)
begin
D <= (others => '0'); -- all bits 0
D(n) <= '1'); -- e.g. n = 0 => set bit 0, n = 1
=
set bit 1
D(7 downto 0) <= X"FF";
end process;

This is not equivalent. What about the carry when n < 8
?
Click to expand...
Sorry, brain failure - luckily Jon has answered it for me!

I must work out how to get outlook express to wrap
sensibly as well...

regards

Alan



--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification *
Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood,
Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views
which are not the
views of Doulos Ltd., unless specifically stated.
 
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