Validity of if generate branch

[Mario Trentini]

Hello,

I would like to know how both branches of a if generate shall be valid
in verilog.

Both branches shall have a valid verilog syntax for correct parsing, but
what about elaboration issue with other modules ?

For instance, with this example :

L:01 module test (a, b);
L:02 input a;
L:03 output b;
L:04
L:05 parameter with_enable = 0;
L:06
L:07 generate
L:08 if (with_enable)
L:09 begin
L:10 sub_module sub_module (
L:11 .enable (1'b1),
L:12 .data_in (a),
L:13 .data_out (b)
L:14 );
L:15 end
L:16 else
L:17 begin
L:18 sub_module sub_module (
L:19 .data_in (a),
L:20 .data_out (b)
L:21 );
L:22 end
L:23 endgenerate
L:24
L:25 endmodule
L:26
L:27 module sub_module(data_in, data_out);
L:28
L:29 input data_in;
L:30 output data_out;
L:31
L:32 assign data_out = ~data_in;
L:33
L:34 endmodule


This code is correct as long as with_enable is 0, and it is not if
with_enable is 1.
In case this module is used in a design with with_enable=0, is it
legitimate for a tool to return an error at line 11 ?
Or is it normal for a tool to not return an error on such construction ?

And, what if the parameter with_enable is a localparam ?

I encounter both behavior in different tools and I would like to know if
the construction is not valid and which tools shall be fixed.

Regards

Mario