Validating parameter inside a module

[SG]

In a verilog module I want to set some registers based on the clock frequency. I also want to validate the clock frequency to be either 50 MHz or 100MHz. If not, then I want to fail the compile. How do I do this using verilog 2001 ?

SG

 

[Mark Curry]

In article <19832207.1071.1331521687488.JavaMail.geo-discussion-forums@pbcql4>,
SG <sumit0973@gmail.com> wrote:

In a verilog module I want to set some registers based on the clock frequency.
I also want to validate the clock frequency to be either 50 MHz or 100MHz. If
not, then I want to fail the compile. How do I do this using verilog 2001 ?

SG

SG,

We pass the clock frequency down via a parameter.
This is often more convenient as an integer parameter of the PERIOD expressed
in PS:

parameter CLK_PERIOD_PS = 10000;

Then, you can add some checks:

initial
if( ( CLK_PERIOD_PS < 10000 ) | ( CLK_PERIOD_PS > 20000 ) )
begin
$display( "*** CONFIG ERROR *** Clk period of out range!" );
$finish;
end

This will cause your sim to exit. For synthesis, XST (Xilinx) will also stop
the compile. Dunno about other synthesizers.

Now, if you need to measure the frequency of an incoming clock, that's an
entirely different problem... (And a bit more difficuilt to solve).

--Mark