V6 SerDes simulation

[General Schvantzkoph]

I'm trying to simulate the GTX SerDes, I've tried both NCverilog and
Questa. The outputs of the GTXE1 model are all tristate, is there a trick
to simulating the V6 SerDes models?

 

[Muzaffer Kal]

On 27 Jan 2011 22:19:01 GMT, General Schvantzkoph
<schvantzkoph@yahoo.com> wrote:

I'm trying to simulate the GTX SerDes, I've tried both NCverilog and
Questa. The outputs of the GTXE1 model are all tristate, is there a trick
to simulating the V6 SerDes models?

Are you resetting it? Is the clock input good? Is the data input good?

--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

[maxascent]

I would of thought that coregen would create a simulation testbench for yo
which would just work. Have you not tried that?

Jon

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