V4 teaser

J

Jan Gray

Guest
"Xilinx ... today unveiled details of its Virtex-4 (TM) Platform FPGAs..."

Scant details -- sans data sheets, this event is closer to a second wave of
ASMBL teaser PR than a product launch.

Some interesting tidbits, though. Up to 200 kLUTs, enhanced DSP, PPC APU
port, and apparently evolution, not revolution, with respect to CLB
architecture (*). All good.

EE Times reports 14 devices "in the works" (compare to ~11 V2 products and
10+2 follow-ons). Spread over three family variants, that could mean steeper
than historic device capacity steps within some variants. We'll see.

http://www.xilinx.com/company/press/kits/v4_arch/v4_finalwhitepaper4.pdf,
first paragraph:
"Xilinx had already established itself with numerous implementations of
FPGA-based RISC processors and processor cores, with the earliest example
being Philip Freidin's RISC4005/R16 FPGA processor implementation in 1991."

Jan Gray
Gray Research LLC

-----
(*) Perhaps I read too much into the statements of "Up to 7 input
functions/CLB" and "Full support for all Virtex-II Series features".
 
I wrote "Up to 200 kLUTs", but to be precise, the Xilinx press release
states "With up to 200,000 logic cells...".

Not the same thing, LUTs and logic cells. Sorry about that.

Jan Gray
Gray Research LLC
 
Jan Gray wrote:
I wrote "Up to 200 kLUTs", but to be precise, the Xilinx press release
states "With up to 200,000 logic cells...".

Not the same thing, LUTs and logic cells. Sorry about that.
Click to expand...
Are you talking about the 12% inflation factor, or are logic cells
actually something different than a LUT plus a FF? Anyone know what a
logic cell is?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
rickman wrote:
Jan Gray wrote:

I wrote "Up to 200 kLUTs", but to be precise, the Xilinx press release
states "With up to 200,000 logic cells...".

Not the same thing, LUTs and logic cells. Sorry about that.


Are you talking about the 12% inflation factor, or are logic cells
actually something different than a LUT plus a FF? Anyone know what a
logic cell is?
Click to expand...
Xilinx's definition is:

"Logic cell = One 4-input Look Up Table (LUT) + Flip Flop + Carry Logic"

If I recall, they are not including the MUXFx's that are after the LUTs.
As you correctly surmised, Xilinx feels those are worth an additional
12% (so there are ~12% more logic cells than there are LUTs).

Are they right? The high speed (311 MHz, therefore heavily pipelined)
design I'm working on right now uses

457 MUXF's plus
6170 LUTs

So they're only off by 50% or so. A slower design that isn't nearly as
well pipelined uses:

2618 MUXF's plus
22832 LUTs

Which is noticeably less than 12%, but closer to their marketing number.

Marc
 
Being an engineer myself, I've never much liked the difference between LUTs
and logic cells.

However, the story goes beyond just MUXFs. The Xilinx LUT delivers a few
other unique capabilities ...

* 16x1 distributed RAM, either single-ported or with separate read/write and
read-only ports
- Roughly equivalent to 16 'D' flip-flops, two 16:1 output select MUXs,
and 16 4-input decode gates

* 16-bit serial-in, serial-out shift register with tap select output
- Roughly equivalent to 16 'D' flip-flops, and 16:1 output select MUX

Add that into the mix, I believe it comes out well ahead of the 12% fudge
factor. It is admittedly a fudge factor because not every design (okay,
except for Ray Andraka ;) will use every LUT as distributed RAM or shift
registers.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC

"Marc Randolph" <mrand@my-deja.com> wrote in message
news:c9mdnbfiOc81YVvdRVn-uA@comcast.com...
rickman wrote:
Jan Gray wrote:

I wrote "Up to 200 kLUTs", but to be precise, the Xilinx press release
states "With up to 200,000 logic cells...".

Not the same thing, LUTs and logic cells. Sorry about that.


Are you talking about the 12% inflation factor, or are logic cells
actually something different than a LUT plus a FF? Anyone know what a
logic cell is?

Xilinx's definition is:

"Logic cell = One 4-input Look Up Table (LUT) + Flip Flop + Carry Logic"

If I recall, they are not including the MUXFx's that are after the LUTs.
As you correctly surmised, Xilinx feels those are worth an additional
12% (so there are ~12% more logic cells than there are LUTs).

Are they right? The high speed (311 MHz, therefore heavily pipelined)
design I'm working on right now uses

457 MUXF's plus
6170 LUTs

So they're only off by 50% or so. A slower design that isn't nearly as
well pipelined uses:

2618 MUXF's plus
22832 LUTs

Which is noticeably less than 12%, but closer to their marketing number.

Marc
Click to expand...
 
"Steven K. Knapp" wrote:
Being an engineer myself, I've never much liked the difference between LUTs
and logic cells.

However, the story goes beyond just MUXFs. The Xilinx LUT delivers a few
other unique capabilities ...

* 16x1 distributed RAM, either single-ported or with separate read/write and
read-only ports
- Roughly equivalent to 16 'D' flip-flops, two 16:1 output select MUXs,
and 16 4-input decode gates

* 16-bit serial-in, serial-out shift register with tap select output
- Roughly equivalent to 16 'D' flip-flops, and 16:1 output select MUX

Add that into the mix, I believe it comes out well ahead of the 12% fudge
factor. It is admittedly a fudge factor because not every design (okay,
except for Ray Andraka ;) will use every LUT as distributed RAM or shift
registers.
Click to expand...
That may well be, but I think most engineers that are using your parts
understand the advantages of the Xilinx CLB design. How about if you
limit the numbers in your data sheets to just the LUT count and drop
marketing terms like "Logic Cells" which have no meaning in a data sheet
since they are an *interpretation* and will vary according to the
design.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
How about a 32 macrocell....x I mean LUT device. With an on board flash
memory you'd find a market. If Xilinx had it's own packaging house, like
Microchip, such a device might prove to be juicy, so to speak.

Hul

Steven K. Knapp <steve.knappNO#SPAM@xilinx.com> wrote:
Being an engineer myself, I've never much liked the difference between LUTs
and logic cells.

However, the story goes beyond just MUXFs. The Xilinx LUT delivers a few
other unique capabilities ...

* 16x1 distributed RAM, either single-ported or with separate read/write and
read-only ports
- Roughly equivalent to 16 'D' flip-flops, two 16:1 output select MUXs,
and 16 4-input decode gates

* 16-bit serial-in, serial-out shift register with tap select output
- Roughly equivalent to 16 'D' flip-flops, and 16:1 output select MUX

Add that into the mix, I believe it comes out well ahead of the 12% fudge
factor. It is admittedly a fudge factor because not every design (okay,
except for Ray Andraka ;) will use every LUT as distributed RAM or shift
registers.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC

"Marc Randolph" <mrand@my-deja.com> wrote in message
news:c9mdnbfiOc81YVvdRVn-uA@comcast.com...
rickman wrote:
Jan Gray wrote:

I wrote "Up to 200 kLUTs", but to be precise, the Xilinx press release
states "With up to 200,000 logic cells...".

Not the same thing, LUTs and logic cells. Sorry about that.


Are you talking about the 12% inflation factor, or are logic cells
actually something different than a LUT plus a FF? Anyone know what a
logic cell is?

Xilinx's definition is:

"Logic cell = One 4-input Look Up Table (LUT) + Flip Flop + Carry Logic"

If I recall, they are not including the MUXFx's that are after the LUTs.
As you correctly surmised, Xilinx feels those are worth an additional
12% (so there are ~12% more logic cells than there are LUTs).

Are they right? The high speed (311 MHz, therefore heavily pipelined)
design I'm working on right now uses

457 MUXF's plus
6170 LUTs

So they're only off by 50% or so. A slower design that isn't nearly as
well pipelined uses:

2618 MUXF's plus
22832 LUTs

Which is noticeably less than 12%, but closer to their marketing number.

Marc
Click to expand...
 
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