V2Pro config problems with HSTL_II_DCI pads...

[John Providenza]

I'm seeing a problem configuring a V2Pro-7 part when I add
HSTL_II_DCI pads to my design. The bit stream downloads,
but I don't get a 'done' signal. If I change the pads to
be HSTL_II, the bitstream downloads OK. I'm also using
some HSTL_I_DCI pads, but these don't seem to cause a
problem.

Anyone else seen and/or worked-around this problem?

Thanks!

John P.

 

[Chen Wei Tseng]

John,

Assuming you're using 6.2i software, when DCI IOs are used it's possible
for the FPGA to wait and try to match DCI before DCI is released. You
can tell from your bgn file if match cycle is set prior to the done
cycle. You can also set bitgen options to not wait for DCI and give that
a try.

http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/dev/dev0125_18.html

Regards, Wei
Xilinx Applications

John Providenza wrote:

I'm seeing a problem configuring a V2Pro-7 part when I add
HSTL_II_DCI pads to my design. The bit stream downloads,
but I don't get a 'done' signal. If I change the pads to
be HSTL_II, the bitstream downloads OK. I'm also using
some HSTL_I_DCI pads, but these don't seem to cause a
problem.

Anyone else seen and/or worked-around this problem?

Thanks!

John P.