V2K doubt...

[Ron]

Is multidimensional arrays allowed to be used as ports in Verilog 2000 syntax??

Ex. input wire [31:0] dummy [31:0];

 

[Steven Sharp]

ronjacob@gmail.com (Ron) wrote in message news:<84a4021f.0408232247.759540c@posting.google.com>...

Is multidimensional arrays allowed to be used as ports in Verilog 2000 syntax??

Ex. input wire [31:0] dummy [31:0];

No, they are not. Ports are still restricted to being vectors.

Arrays of nets are pretty much just a way of organizing a group of vector
nets locally inside a module. They are most useful with generate-for-loops,
which provide an organized way of setting up connections for the organized
group of vectors.

References to arrays must select a single element, which can then be
operated on. There are no operations or references to entire arrays, and
that includes port expressions.

 

[Shalom Bresticker]

No.

Shalom


Ron wrote:

Is multidimensional arrays allowed to be used as ports in Verilog 2000 syntax??

Ex. input wire [31:0] dummy [31:0];

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