Using Xilinx libraries in Verilog code..

[kb33]

Hi,

I am trying to download a verilog design onto a Xilinx Virtex2 FPGA
without much success uptil now. Based on what I see in one of the
example VHDL code that came with the PCI board, I suspect that I have
to include some Virtex libraries to make my Verilog code recognise the
pad interface signals of the FPGA chip.

The VHDL (example) code looks like this:

-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

-- Wildstar System Libraries -
library WSII_SYSTEM;
use WSII_SYSTEM.AMS_package.all;
use WSII_SYSTEM.AMS_IO_package.all;

-- WildstarII PE Libraries --
library WSII_PE_Lib;
use WSII_PE_Lib.PE_Package.all;
--use WSII_PE_Lib.IO_Package.all;

library WSII_Xilinx_Lib;
use WSII_Xilinx_Lib.VIRTEX2.all;
use WSII_Xilinx_Lib.VIRTEX.all;

The code also has the following alias defined for the clock input:

alias I_Clk : std_logic is LAD_Bus_In.RxClk_In.Clk;

SO in case of Verilog, how would these issues be taken care of ? How
can I specifically map my input and output signals to the desired pins
on the processing element pad? I thought that the Synthesis and Place
and route would automatically take care of this, but that doesn't seem
to be that case.

kb33