using VHDL configurations in a verilog test bench

[Andy Luotto]

hi there
i am verifying a VHDL RTL where i want to swap different
implementations of the same entity (i want to replace huge dsp blocks
by transparent feedthru datapath to manage a high complexity design)
i'd like to do this is a verilog testbench and i waoder how to
'select' the proper architecture.
i know that verilog, since 2001 release, can specificy configurations
and i ask know if it is possible to mix language at this level too

i am using cadence ncsim

thanks in advance to who'll reply

 

[Mike Treseler]

Andy Luotto wrote:

i am verifying a VHDL RTL where i want to swap different
implementations of the same entity (i want to replace huge dsp blocks
by transparent feedthru datapath to manage a high complexity design)
i'd like to do this is a verilog testbench and i waoder how to
'select' the proper architecture.
i know that verilog, since 2001 release, can specificy configurations
and i ask know if it is possible to mix language at this level too

No. I would write scripts
to compile the swapped modules/entities
as required for each implementation.

-- Mike Treseler