Using VerilogIn

[Riad KACED]

Hi Dinac,

You are on the right track.
The best for you is read the following documentation:
"VerilogŽ In for Design Framework II™ User Guide and Reference". This
document is available in your cadence stream:
$CDSHOME/doc/verinuser/verinuser.pdf

I would like to highlight some points that might be useful for you.

1. References Libraries
put in the list (space separated) of all the digital core libraries of
all the primitives used in your veriliog code. There will be cells
missing otherwise.

2. Import structural modules as:
I wold advice to set it at "schematic & functional" to make a
schematic view for LVS and a functional view for simulation.

3. Power/Ground Net name:
If your verilog code contains nets named VDD/GND then verilogIn will
import them as global nets VDD!/GND!. If you wish to avoid this
behaviour then put arbitrary names in these fields.

That said, the most accurate and up to date information about
verilogIn id available in the document mentioned above.

Cheers,
Riad.

 

[dinac]

hi Riad, all,

Thanks for your reply.
it was really helpful.

i have more clarification about the The Reference Library :? I could
not understand

The Digital Simulation uses standard cells and which are typically of
format " .lib or .db " and I used them to synthesise my design.
and I have them.

Should I generate this Reference Library from this .lib standard-
cell. ?

Thanks a lot
It will be really helpfull

 

[Riad KACED]

Hi Dinac,

The ref libs are simply the cds libraries where your standard cells
are defined. Simple as that !
You should declare the stand cell libraries in your cds.lib so you can
see them in your cadence session along with the other technology and
design libraries.
In other words, your ref libs for verilog import are those you have
used for synthesis. You just need to load them into DFII using the
cds.lib

Does this help ?

Cheers,
Riad.

 

[dinac]

Hi Riad,/all,

Thanks for your help again.

I did define the library ".lib" location in cds.lib. but when i parse
this verilog netlist i get few errors.

VerilogIn: *W,31 => Module X in FSM_file not defined.Module FSM_file
will be imported as functional.

VerilogIn: *W,101 => Could not find symbol master for instance
XY .Functional view won't have this instance.

Most of the Modules showed this error.

thanks

cheers
dinac

 

[Riad KACED]

Hi Dinac,

Let me explain differently.
The reference library I'm talking about is a A Cadence DFII Library,
CDBA or OA. I'm not talking about any .lib file.
The reference library should be known in your Cadence session, along
with other libs: analogLibb, basic,YourPdkTechLibb ... etc.
dard cell libraries as reference.

There is one more thing I missed to mention.
You may need to specify the names of the Verilog files needed to
compile the design. In other words, specifyVerilogrilog file that
defines your standard cell primitives. This file veriloglly provided
within the standard cell library. It is a verilog file that defines
all the standards cells. I guess it is thverilogfile you were talking
about eventhough I use to know these kind of files as .v
Never mind the neventhoughis file looks like it defines all the
modules for your cells, then please add this file into the '-v
options' of the verilogIn GUI. Please look a the doc for more
information.

To summarize:
The VerilogFile to import does contain your design/modules which makes
use of standard Cells (primitives). These primitives are defined in
your StandrdLib file you need to specify in the '-V Options field'.
When verilogIn creates your cds Schematic, the primitive symbols will
be picked up from the reference libraries you've mentioned in the
GUI.

Hope this will help you to get rid of this ;-)
Cheers,
Riad.

 

[dinac]

Hi Riad / all,

Thanks a lot.... i really appreciate your help.

I finally can see my Gate-level Netlist in my Cadence cell view.


1. I searched for the Reference Library, its called "CDK" which i
found in my foundry.
This CDK was Present in Directory structure ../digital/Back_End/
CDK/
it had a cds.lib file too in that directory.

2. -V option i provided the link of the standard-cell file in verilog
format. ".V"


I found few errors, mentioning the verilog
" Verilog definition for module AN2D4 was not found. Using lib
'techlib' cell 'AN2D4' view 'symbol' as its symbol.

But i guess I could discard this.


Thanks a lot Again

cheers
dinac

 

[Riad KACED]

Hi Dinac,

I won't ignore this error myself ...
Means your are missing the verilog file that declares this primitive.
Just find it and add it into the -V options list
I'm very cautious and try to get everything clean (neither errors nor
warnings) as much as possible.

Cheers,
Riad.

 

[dinac]

Hi Riad/all,

sorry got few more doubts.

1. I got the gate-level netlist into the cell-view.

2. But is i see the Reference Library provided by the , has lot of
bugs.
The length of the nch and pch for each of the transistors were
missing , and even some width. Are these normal?
I had to edit my netlist and made my design running.

3. The Verilog modules,
I used the standard-cell .v format given by the foundry.
To check the modules. i did a Gate-level Simulation of my Design
in modelsim, to check on the primitives.
i did not have any problem there.
And i used this same .v techfile in verilogin , -v /$path/
techfile.v

Hope I am Referring to the correct File in -v ?

Thanks Again

cheers
dinac

 

[Riad KACED]

Hi Dinac,

I can't help you on technology related questions I'm afraid. You
better get in touch with your PDK provider. If you think there is a
bug somewhere, it's always better to get your PDK provider involved
instead of fiddling with the files on your own.

Cheers,
Riad.

 

[Riad KACED]

Hi Dinac,

I can't help you on technology related questions I'm afraid. You
better get in touch with your PDK provider. If you think there is a
bug somewhere, it's always better to get your PDK provider involved
instead of fiddling with the files on your own.

Cheers,
Riad