Using Verilog to embed the synthesis date and time

[John Providenza]

Does anyone have a simple way to embed the date and time
that a module is compiled into a wire or register in Verilog?

I could use a Perl script to create an `include file with the
proper `define statements, but I'm wondering if anyone has
a cute way to do this purely in Verilog.

FYI - I'm using Xilinx XST for synthesis.

Thanks!

John P

 

[Symon]

John,
No, I've always done this with Perl. I've also used Perl & Data2MEM to
include the P&R time into the download bitstream. The times are loaded into
a BlockRAM which is the character storage for my debug VGA driver. Very
useful when working with those (sometimes forgetful, bless 'em) software
guys!
Cheers, Syms.
"John Providenza" <johnp3+nospam@probo.com> wrote in message
news:349ef8f4.0407190727.2a35fff9@posting.google.com...

Does anyone have a simple way to embed the date and time
that a module is compiled into a wire or register in Verilog?

I could use a Perl script to create an `include file with the
proper `define statements, but I'm wondering if anyone has
a cute way to do this purely in Verilog.

FYI - I'm using Xilinx XST for synthesis.

Thanks!

John P

 

[Hal Murray]

No, I've always done this with Perl. I've also used Perl & Data2MEM to
include the P&R time into the download bitstream. The times are loaded into
a BlockRAM which is the character storage for my debug VGA driver. Very
useful when working with those (sometimes forgetful, bless 'em) software
guys!

You can also use cpp for hacks like this.

It's the c pre-processor that processes #include and #ifdef
and #define and such.

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[Allan Herriman]

On 19 Jul 2004 08:27:08 -0700, johnp3+nospam@probo.com (John
Providenza) wrote:

Does anyone have a simple way to embed the date and time
that a module is compiled into a wire or register in Verilog?

I could use a Perl script to create an `include file with the
proper `define statements, but I'm wondering if anyone has
a cute way to do this purely in Verilog.

FYI - I'm using Xilinx XST for synthesis.

Another solution that you may not have considered is to put the
timestamp and version information in a header prepended to the
download image. This is trivial to do as part of your build process,
and avoids the need to have any extra information inside the FPGA
itself.

(Obviously this only works if the FPGA is downloaded from a cpu - the
cpu will read and strip the version and timestamp info before
downloading it into the fpga.)

I (and others) developed something similar when I was at Agilent. We
ended up with a lot of information in the headers, including:
- An ID that was unique for each download.
- The name of the person who generated the download file (which came
from the username on the computer).
- The part number of the FPGA (extracted from the EDIF file).
- Date stamps for synthesis and PAR (extracted from the EDIF and the
PAR report file).
- The version number of the synthesiser and PAR tools (extracted from
the respective report files).

All of this was done automatically by the build script, which meant
that all fpga download image files had complete traceability back to
the exact source files and tool versions. This made bug finding much
easier (particularly tool bugs).

Regards,
Allan.

 

[Martin Thompson]

johnp3+nospam@probo.com (John Providenza) writes:

Does anyone have a simple way to embed the date and time
that a module is compiled into a wire or register in Verilog?

I could use a Perl script to create an `include file with the
proper `define statements, but I'm wondering if anyone has
a cute way to do this purely in Verilog.

FYI - I'm using Xilinx XST for synthesis.

I've embedded the place and route time (year, month, day, hour) in the
bitstream in the past as the USERCODE 0xyymmddhh

And embedded the synthesis time in the "HDL" by overriding a top-level
generic with a synplify TCL script, which is an idea I saw mentioned
somewhere in this NG, or maybe in comp.arch.vhdl.

Cheers,
Martin


--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

 

[Symon]

"Martin Thompson" <martin.j.thompson@trw.com> wrote in message
news:u3c3m28dk.fsf@trw.com...

johnp3+nospam@probo.com (John Providenza) writes:

I've embedded the place and route time (year, month, day, hour) in the
bitstream in the past as the USERCODE 0xyymmddhh

Neat!!

 

[John Providenza]

Well, I've ended up using a perl script to modify a line
of code in my main include file. I have to remember to
run the script, but it's painless other than that.

I decided to use the Unix "epoch" style timestamp in the
include file. Trivial C code can decode it and it is a
simple 32 bit value to assign to a regr or wire in Verilog.

The C code to print it is like:
// 1st, you need to read the value into 'tmp32', then....
printf("Verilog build date was %s", ctime(&tmp32) );


In the include file I have:
parameter BLD_EPOCH = 32'd1090435314;

The Perl script that updates the line is:
#!/usr/bin/perl -w
#
# SET_EPOCH.PL
# script to update the BLD_EPOCH parameter in the main include file
#

# define the include file and a tmp verion of it....
my $file = "../common_v/po_include.v";
my $tmpfile = $file . "2";

my $found = 0;

my $target_string = "^\\s*parameter\\s+BLD_EPOCH\\s+=\\s+32'd";

my $epoch = time();

# open the original file for reading...
open(ORIG, "<$file") || die "couldn't open $file for reading\n";
open(NEW, ">$tmpfile") || die "couldn't open $tmpfile for writing\n";

# loop copying lines....
while (<ORIG&gt {
if (/$target_string/) {
s/32'd.*$/32'd$epoch;/;
print "setting \n\t$_\n";
$found = 1;
}
print NEW $_;
}

close(NEW);
close(ORIG);

if ($found) {
rename($tmpfile, $file) || die "couldn't rename $tmpfile to $file\n";
} else {
unlink($tmpfile);
die "didn't find string /$target_string/\n";
}


I hope this amuses/helps others!

John P