using the 'include directive in verilog

[Pankaj]

Hello,
Please could someone tell me the exact sequence of steps that need to
be followed while including any verilog file into the main verilog
file and how to correlate the output of the included file to the
output (or monitor statement) of the main file where it has been
included.
My problem is even after including the verilog file I am not able to
correlate the output of the included file to the output of the main
file.

thanks,
Pankaj

 

[Ajeetha (www.noveldv.com)]

On Feb 20, 2:34 pm, "Pankaj" <pankajna...@gmail.com> wrote:

Hello,
Please could someone tell me the exact sequence of steps that need to
be followed while including any verilog file into the main verilog
file and how to correlate the output of the included file to the
output (or monitor statement) of the main file where it has been
included.
My problem is even after including the verilog file I am not able to
correlate the output of the included file to the output of the main
file.

thanks,
Pankaj

Pankaj,
Can you be more precise with your problem statement? Maybe show a
small testcase? Something like:

inc.v file

task my_task();
$display ("From include file");
endtask

main.v file
module main();
`include "inc.v"
initial my_task();
endmodule

The above should work (didn't check though), provide details on

I am not able to
correlate the output of the included file to the output of the main
file.

Only then we can help you better.

Good luck
Ajeetha, CVC
www.noveldv.com

 

[parag_paul@hotmail.com]

On Feb 20, 6:00 pm, "Ajeetha (www.noveldv.com)" <ajee...@gmail.com>
wrote:

On Feb 20, 2:34 pm, "Pankaj" <pankajna...@gmail.com> wrote:

Hello,
Please could someone tell me the exact sequence of steps that need to
be followed while including any verilog file into the main verilog
file and how to correlate the output of the included file to the
output (or monitor statement) of the main file where it has been
included.
My problem is even after including the verilog file I am not able to
correlate the output of the included file to the output of the main
file.

thanks,
Pankaj

Pankaj,
Can you be more precise with your problem statement? Maybe show a
small testcase? Something like:

inc.v file

task my_task();
$display ("From include file");
endtask

main.v file
module main();
`include "inc.v"
initial my_task();
endmodule

The above should work (didn't check though), provide details on

I am not able to
correlate the output of the included file to the output of the main
file.

Only then we can help you better.

Good luck
Ajeetha, CVCwww.noveldv.com

Hi Pankaj ,
I will just give you a hint. If you compile C files, there is
something called the -E flag. Similarly, the 'include does nothing but
exactly cut and paste all the code inside the file as soon you add the
'include <filenam> anywhere in your file.

Lets say
we have a file p2.v
----------------------------------
reg b,c;
initial
#1
$display(" the value of b from the file p2.v is %d\n", b);


And another file p3.v
------------------------------------
module top;
`include "p2.v"
initial

begin
b=1;
end
endmodule

Now if you compile p3.v <---- you will realize what you are saying .

If you can generate tokens.v after ( if you are using Synopsys
tools )
You see that the tokens.v looks like the following
---------------------------------------------------------

`portcoerce
`inline
// No timescale specified
module top;

reg b;
reg c;

initial #(1) $display(" the value of b from the file p2.v is %d
\n", b);
initial begin
b = 1;
end
endmodule



That is it has exaclty cut and pasted all the code from p2.v to the
point where we had used the 'include