using the FALLING constrain with cores (coregen)

[Patrice Favreau]

I am using Xilinx ISE6.1.01i

I would like to use a falling clock on a core (binary counter),

This core does not have a falling edge "selection" such as the BRAM...

I tried the use the FALLING constrain with no success.(no effect)

My question is : is it possible to use the FALLING constrain with cores?

Thanks

Patrice Favreau