using signal as clk source

T

Tobias Möglich

Guest
Hello

I use Xilinx ISE Foundation 6.1.

Is it possible to use a signal as a clk source?
The problem I got is: if I assign a special Pin (LOC constraints), the
mapper tool claims:

"ERROR:MapLib:93 - Illegal LOC on IPAD symbol "IOSTRB_DSP" or BUFGP
symbol
"IOSTRB_DSP_BUFGP" (output signal=IOSTRB_DSP_BUFGP), IPAD-IBUFG
should only
be LOCed to GCLKIOB site"


(-> the signal_name is IOSTRB_DSP)

If I don't make a constraint for the signal, the report say: used: Type:
GCLKIOB.
Why does ISE not connect it to an GCLKIOB as I put in a LOC constraint
for the signal IOSTRB_DSP?

I have to tell "place & route" where to connect the signal to.
What should be filled in the constraint file?
Or what should be chosen in PACE?

Thanks for any help.


Tobias Möglich
 
BUFGP is IBUFG + BUFG, and IBUFG can only be used by signal from GCLK pins.

just use BUFG only.
"Tobias Möglich" <Tobias.Moeglich@gmx.net>
??????:4002FAC9.24DEF52E@gmx.net...
Hello

I use Xilinx ISE Foundation 6.1.

Is it possible to use a signal as a clk source?
The problem I got is: if I assign a special Pin (LOC constraints), the
mapper tool claims:

"ERROR:MapLib:93 - Illegal LOC on IPAD symbol "IOSTRB_DSP" or BUFGP
symbol
"IOSTRB_DSP_BUFGP" (output signal=IOSTRB_DSP_BUFGP), IPAD-IBUFG
should only
be LOCed to GCLKIOB site"


(-> the signal_name is IOSTRB_DSP)

If I don't make a constraint for the signal, the report say: used: Type:
GCLKIOB.
Why does ISE not connect it to an GCLKIOB as I put in a LOC constraint
for the signal IOSTRB_DSP?

I have to tell "place & route" where to connect the signal to.
What should be filled in the constraint file?
Or what should be chosen in PACE?

Thanks for any help.


Tobias Möglich
Click to expand...
 
I use the Spartan-IIE from Xilinx
BUFG ist not available for this device. What can I use instead?

And how do I have to implement it in the ucf-file or in the source file
(vhd-file)?

Tobias.
 
The BUFG primitive is available for Spartan-IIE. Which tool or
documentation indicates that it not available? Depending on which synthesis
tool you use, BUFG may be automatically instantiated in your design.

If you want to directly instantiate a BUFG primitive, here the template
provided by the "Language Templates" option inside the ISE 6.1i Project
Navigator. To open the templates, start Project Navigator and click
Edit --> Language Templates.

Expand the "VHDL" item in the selection tree, then "Component
Instantiation", the "Global Clock Buffer", then "BUFG".

Note: You can also invoke Language templates by clicking the "light bulb"
icon in the upper right menu bar.

Here is the Language Templates template for the global clock buffer.
____________________________________

-Instantiating BUFGP on Input Port
-- INPUT_PORT: in std_logic;

--**Insert the following between the
-- 'architecture' and 'begin' keywords**

component BUFGP
port (I: in std_logic; O: out std_logic);
end component;

--**Insert the following after the 'begin' keyword**

signal CLK_SIG: std_logic;
U1: BUFGP port map (I => INPUT_PORT, O => CLK_SIG);

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC

"Tobias Möglich" <Tobias.Moeglich@gmx.net> wrote in message
news:4003F514.3258F24B@gmx.net...
I use the Spartan-IIE from Xilinx
BUFG ist not available for this device. What can I use instead?

And how do I have to implement it in the ucf-file or in the source file
(vhd-file)?

Tobias.
Click to expand...
 
Here is what I learned from our applications group:

The BUFG primitive is available for Spartan-IIE. Which tool or
documentation indicates that it not available? Depending on which synthesis
tool you use, BUFG may be automatically instantiated in your design.

If you want to directly instantiate a BUFG primitive, here the template
provided by the "Language Templates" option inside the ISE 6.1i Project
Navigator. To open the templates, start Project Navigator and click
Edit --> Language Templates.

Expand the "VHDL" item in the selection tree, then "Component
Instantiation", the "Global Clock Buffer", then "BUFG".

Note: You can also invoke Language templates by clicking the "light bulb"
icon in the upper right menu bar.

Here is the Language Templates template for the global clock buffer.
____________________________________

-Instantiating BUFGP on Input Port
-- INPUT_PORT: in std_logic;

--**Insert the following between the
-- 'architecture' and 'begin' keywords**

component BUFGP
port (I: in std_logic; O: out std_logic);
end component;

--**Insert the following after the 'begin' keyword**

signal CLK_SIG: std_logic;
U1: BUFGP port map (I => INPUT_PORT, O => CLK_SIG);

=============================
Tobias Möglich wrote:
I use the Spartan-IIE from Xilinx
BUFG ist not available for this device. What can I use instead?

And how do I have to implement it in the ucf-file or in the source file
(vhd-file)?

Tobias.
Click to expand...
 
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