Using reset

L

Luiz Gustavo

Guest
This a part of my code:

//generate bit-counter
always @(posedge clk or posedge rst)
if(rst)begin
bit_cntm <= 3'b111;
mem_adr_master <= 3'b000;
end
else
bit_cntm <= bit_cntm - 3'h1;

//generate access done signal
always @(posedge clk)
ldm <= ~(|bit_cntm);

always @(negedge clk)
if (ldm)
begin
mem_in_master[mem_adr_master] <= srim;
master_out <= mem_in_master[mem_adr_master];
mem_adr_master <= mem_adr_master + 1'b1;
end

And this is the error by Quartus II:

Can't resolve multiple constant drivers for net mem_adr[2] in line
"if(rst)begin".
Constant driver in line "if (ldm)".

When I comment the line "mem_adr_master <= 3'b000;" the code
compilation is well...

Obs.:
reg [2:0] bit_cntm;
reg [2:0] mem_adr_master;
input clk, rst;
reg [7:0] mem_in_master [7:0];
reg [7:0] mem_out_master [7:0];
reg srim;
reg ldm;

Some idea?
Thank's!
 
The error message
---
Can't resolve multiple constant drivers for net mem_adr[2] in line
"if(rst)begin".
---
is related to a signal "mem_addr[*]", which is not in your codes you
posted.
I assume that you tried to recode your code in the post for company
reasons and
you implied "mem_addr_master".

My observations:

In your examples you try to reset the signal "mem_addr_master"
in the 1st always block but use it in the 3rd always block.

Don't do it. Simulators and synthesizer do not like this coding style.
It is best if you drive the signal within one always block, also with
its reset code.
Move the reset code for mem_addr_master to the 3rd always block.

Always reset the signals, providing that you are writing a
"synthesizable" code.

Try to use one edge of the clock overall in your design.
In your codes you are using both edges of the clock.

So your code will be:

---
//generate bit-counter
always @(posedge clk or posedge rst)
if(rst)begin
bit_cntm <= 3'b111;
// mem_adr_master <= 3'b000; // I commented it out
[Utku]
end
else
bit_cntm <= bit_cntm - 3'h1;

//generate access done signal
always @(posedge clk)
if (rst) begin // improvement
suggestion by Utku
ldm <= 0; // improvement
suggestion by Utku
end // improvement
suggestion by Utku
else // improvement
suggestion by Utku
ldm <= ~(|bit_cntm);

always @(negedge clk)
if (rst) begin // improvement
suggestion by Utku
mem_adr_master <= 3'b000; // improvement
suggestion by Utku
master_out <= 0; // improvement
suggestion by Utku
end // improvement
suggestion by Utku
else // improvement
suggestion by Utku
if (ldm)
begin
mem_in_master[mem_adr_master] <= srim;
master_out <= mem_in_master[mem_adr_master];
mem_adr_master <= mem_adr_master + 1'b1;
end
---

Utku

On 22 Feb., 14:25, "Luiz Gustavo" <luizval...@gmail.com> wrote:
This a part of my code:

//generate bit-counter
always @(posedge clk or posedge rst)
if(rst)begin
bit_cntm <= 3'b111;
mem_adr_master <= 3'b000;
end
else
bit_cntm <= bit_cntm - 3'h1;

//generate access done signal
always @(posedge clk)
ldm <= ~(|bit_cntm);

always @(negedge clk)
if (ldm)
begin
mem_in_master[mem_adr_master] <= srim;
master_out <= mem_in_master[mem_adr_master];
mem_adr_master <= mem_adr_master + 1'b1;
end

And this is the error by Quartus II:

Can't resolve multiple constant drivers for net mem_adr[2] in line
"if(rst)begin".
Constant driver in line "if (ldm)".

When I comment the line "mem_adr_master <= 3'b000;" the code
compilation is well...

Obs.:
reg [2:0] bit_cntm;
reg [2:0] mem_adr_master;
input clk, rst;
reg [7:0] mem_in_master [7:0];
reg [7:0] mem_out_master [7:0];
reg srim;
reg ldm;

Some idea?
Thank's!
Click to expand...
 
On Feb 22, 11:26 am, "Utku Özcan" <utku.oz...@gmail.com> wrote:
The error message
---
Can't resolve multiple constant drivers for net mem_adr[2] in line
"if(rst)begin".
---
is related to a signal "mem_addr[*]", which is not in your codes you
posted.
I assume that you tried to recode your code in the post for company
reasons and
you implied "mem_addr_master".

My observations:

In your examples you try to reset the signal "mem_addr_master"
in the 1st always block but use it in the 3rd always block.

Don't do it. Simulators and synthesizer do not like this coding style.
It is best if you drive the signal within one always block, also with
its reset code.
Move the reset code for mem_addr_master to the 3rd always block.

Always reset the signals, providing that you are writing a
"synthesizable" code.

Try to use one edge of the clock overall in your design.
In your codes you are using both edges of the clock.

So your code will be:

---
//generate bit-counter
always @(posedge clk or posedge rst)
if(rst)begin
bit_cntm <= 3'b111;
// mem_adr_master <= 3'b000; // I commented it out
[Utku]
end
else
bit_cntm <= bit_cntm - 3'h1;

//generate access done signal
always @(posedge clk)
if (rst) begin // improvement
suggestion by Utku
ldm <= 0; // improvement
suggestion by Utku
end // improvement
suggestion by Utku
else // improvement
suggestion by Utku
ldm <= ~(|bit_cntm);

always @(negedge clk)
if (rst) begin // improvement
suggestion by Utku
mem_adr_master <= 3'b000; // improvement
suggestion by Utku
master_out <= 0; // improvement
suggestion by Utku
end // improvement
suggestion by Utku
else // improvement
suggestion by Utku
if (ldm)
begin
mem_in_master[mem_adr_master] <= srim;
master_out <= mem_in_master[mem_adr_master];
mem_adr_master <= mem_adr_master + 1'b1;
end
---

Utku

On 22 Feb., 14:25, "Luiz Gustavo" <luizval...@gmail.com> wrote:

This a part of my code:

//generate bit-counter
always @(posedge clk or posedge rst)
if(rst)begin
bit_cntm <= 3'b111;
mem_adr_master <= 3'b000;
end
else
bit_cntm <= bit_cntm - 3'h1;

//generate access done signal
always @(posedge clk)
ldm <= ~(|bit_cntm);

always @(negedge clk)
if (ldm)
begin
mem_in_master[mem_adr_master] <= srim;
master_out <= mem_in_master[mem_adr_master];
mem_adr_master <= mem_adr_master + 1'b1;
end

And this is the error by Quartus II:

Can't resolve multiple constant drivers for net mem_adr[2] in line
"if(rst)begin".
Constant driver in line "if (ldm)".

When I comment the line "mem_adr_master <= 3'b000;" the code
compilation is well...

Obs.:
reg [2:0] bit_cntm;
reg [2:0] mem_adr_master;
input clk, rst;
reg [7:0] mem_in_master [7:0];
reg [7:0] mem_out_master [7:0];
reg srim;
reg ldm;

Some idea?
Thank's!
Click to expand...
Thank you very much!!!
I tested now.. It was ok!!!
 
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