using reg with inout

[nisheethg@gmail.com]

Hello
I m stuck with the follwoing. I want to make port c as inout
and use it in 'always'.But, 'always' needs left hand side to be
register type which is not possible with inout type. Any solutions??

------------------------------------------
module(rd,wr,c,clk);
input rd,wr;
inout [7:0] c;
input clk;
reg [7:0] c;
reg [7:0] data;
always@(rd,wr,posedge clk)
begin
if(clk)
begin
if(rd)
c<=data;
if(wr)
data<=c;
end
end
endmodule
----------------------------------------



Nisheeth

 

[Ralf Hildebrandt]

nisheethg@gmail.com wrote:

I want to make port c as inout

Really? You should use two signals for both directions in your design
and only finally use inout pins at the top level.

and use it in 'always'.But, 'always' needs left hand side to be
register type which is not possible with inout type. Any solutions??

Use an intermediate signal. Assign your values inside the always
statement to this intermediate signal and copy it's content to the port.

Ralf

 

[nisheethg@gmail.com]

Hi
I am converting VHDL code to Verilog. In the VHDL code port c is
buffer with read and write being made to that port. Therefore, I used
inout. I would have used 2 ports, one for read and one for right, but
somehow project constraints doesn't allow me to do that. So I have to
stick to inout.
Ralf I will try your suggestion and will get back to u...

Nisheeth

 

[Ralf Hildebrandt]

nisheethg@gmail.com wrote:

I am converting VHDL code to Verilog. In the VHDL code port c is
buffer with read and write being made to that port.

Using "buffer" is not recommended. You trapped into a pitfall, that
would not occur in VHDL if you would not have used buffer. It is the
common practice in VHDL to use an intermediate signal.

Therefore, I used
inout. I would have used 2 ports, one for read and one for right, but
somehow project constraints doesn't allow me to do that. So I have to
stick to inout.

O.k. - but nevertheless an intermediate signal should be a possible
solution.

Ralf

 

[Peng Cong]

You may write like this:
module sample(rst_n, clk, rd, wr, c);
input rst_n;
input clk;
input rd;
input wr;
inout [7:0] c;
wire [7:0] c;
wire [7:0] data_in;
assign data_in = c;
assign c = rd ? data : 1'bz;

reg [7:0] data;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
data <= 0;
else
if(wr)
data <= data_in;
end

endmodule

"nisheethg@gmail.com" <nisheethg@gmail.com> wrote in
news:1143916282.147074.175570@t31g2000cwb.googlegroups.com:

Hello
I m stuck with the follwoing. I want to make port c as inout
and use it in 'always'.But, 'always' needs left hand side to be
register type which is not possible with inout type. Any solutions??

------------------------------------------
module(rd,wr,c,clk);
input rd,wr;
inout [7:0] c;
input clk;
reg [7:0] c;
reg [7:0] data;
always@(rd,wr,posedge clk)
begin
if(clk)
begin
if(rd)
c<=data;
if(wr)
data<=c;
end
end
endmodule
----------------------------------------



Nisheeth

 

[ngsayjoe@gmail.com]

if you don't want to use an intermediate register, you could try the
following continuous assign statement:

always ...
begin
....
assign c = <something>;
....
end

Joe,
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

nisheethg@gmail.com wrote:

Hello
I m stuck with the follwoing. I want to make port c as inout
and use it in 'always'.But, 'always' needs left hand side to be
register type which is not possible with inout type. Any solutions??

------------------------------------------
module(rd,wr,c,clk);
input rd,wr;
inout [7:0] c;
input clk;
reg [7:0] c;
reg [7:0] data;
always@(rd,wr,posedge clk)
begin
if(clk)
begin
if(rd)
c<=data;
if(wr)
data<=c;
end
end
endmodule
----------------------------------------



Nisheeth

 

[nisheethg@gmail.com]

Hello
I think Peng cong code should work but simulator is not
showing proper results. I am using Xilinx ISE 7.1 . I am using
testbench generation tool provided in xilinx. I m not sure what is goin
wrong..



Nisheeth