using predefined module in quartusII

[jaytiey]

how to compile vhdl file using predefined module such as lpm_ff or
lpm_ram_dq?

-- R0
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity R0 is
port (
data : in STD_LOGIC_VECTOR(7 downto 0);
clk : in STD_LOGIC;
en : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(7 downto 0)
);
end R0;

architecture R0_arch of R0 is

signal low: STD_LOGIC;
signal temp: STD_LOGIC_VECTOR(7 downto 0);

component LPM_FF
generic (
Note: note := "Flip-Flop";
LPM_WIDTH: integer := 8;
LPM_AVALUE: string := "UNUSED";
LPM_FFTYPE: string := "DFF";
LPM_TYPE: string := "LPM_FF";
LPM_SVALUE: string := "UNUSED";
LPM_HINT: string := "UNUSED"
);
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
CLOCK : in std_logic;
ENABLE : in std_logic;-- := '1';
SLOAD : in std_logic;-- := '0';
SCLR : in std_logic;-- := '0';
SSET : in std_logic;-- := '0';
ALOAD : in std_logic;-- := '0';
ACLR : in std_logic;-- := '0';
ASET : in std_logic;-- := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0)
);



end component;

begin

low <= '0';

U_LPM_FF: LPM_FF
port map (data,clk,en,low,low,low,low,low,low,temp);

q <= temp;

end R0_arch;

after compile..
Error: VHDL error at R0.vhd(22): note type is used but not declared

can someone help me.. tell me what's wrong?

 

[sudhi]

Quartus provides LPM libraries for simulations. You need to compile
those libraries and include in your code as

library lpm;
use lpm."i am not sure what".all
The quartus documentation should include this.

Sudhi