Using LVPECL_25 inputs in Spartan3e problem

G

Giorgos_P

Guest
Hello,

I want to use 24 pairs of LVPECL_25 differential inputs in my design,
at a S3E500 FPGA device. During mapping, ISE gives the following
warnings and removes these inputs:

MapLib:701 - Signal pecl_input_p<23> connected to top level port
pecl_input_p<23> has been removed.
MapLib:701 - Signal pecl_input_n<23> connected to top level port
pecl_input_n<23> has been removed.
...
MapLib:701 - Signal pecl_input_p<23> connected to top level port
pecl_input_p<0> has been removed.
MapLib:701 - Signal pecl_input_n<23> connected to top level port
pecl_input_n<0> has been removed.

The input buffers are instantiated in VHDL like this:

Gen1: for i in 23 downto 0 generate
IBUFDS_inst : IBUFDS generic map (IOSTANDARD => "LVPECL_25")
port map (
O => cmp_in(i), -- Diff_p output (connect
directly to top-level port)
I => pecl_input_p(i), -- Diff_n output (connect
directly to top-level port)
IB => pecl_input_n(i) -- Buffer input
);
end generate Gen1 ;

and in the constraint file it is specified that:

NET "pecl_input_p<0>" LOC = "p57" | IOSTANDARD = LVPECL_25 ;
NET "pecl_input_n<0>" LOC = "p58" | IOSTANDARD = LVPECL_25 ;
...

The "cmp_in" output of the buffer is used and has load connected to
it, that is not removed from optimization steps. The problem seems to
be buffer-related, when I remove the buffer the inputs are not removed
by ISE. I also tried instantiating the buffer with following way,
getting the same results:

Gen1: for i in 23 downto 0 generate
buffer_array : IBUFDS_LVPECL_25 port map
(I=>input_p(i),IB=>input_n(i) , O=>input_int(i));
end generate Gen1 ;

Any ideas?

Thank you in advance for your time,
George
 
Just do a quick search in google for MapLib:701 I found quite a few peopl
who have had the same problem

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
You could try to just create a simple design with 1 buffer driving som
logic with an output and see if that works. If it does then try to build u
to the design you have and see when you get the error.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
On 25 Ďęô, 18:12, "maxascent"
<maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
Just do a quick search in google for MapLib:701 I found quite a few people
who have had the same problem

Jon        

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...

I did that and most of them had the inputs unconnected (no load
connected), while one of them that had a similar problem (not with
pecl buffers but with another standard) solved it by a different
declaration of the buffers, that different declaration is not valid
for my case.

Any ideas guys?

Thank you for your answer Jon
 
On 10/25/2010 3:11 PM, Giorgos_P wrote:
MapLib:701 - Signal pecl_input_p<23> connected to top level port
pecl_input_p<0> has been removed.
MapLib:701 - Signal pecl_input_n<23> connected to top level port
pecl_input_n<0> has been removed.

Hi George,
Click to expand...
This section might be a clue. It seems to be trying to attach bit 23 to
bit 0. Dunno why. FWIW, my code uses 0 to 15 , rather than 15 downto 0,
but that shouldn't make any difference.

Are you sure LVPECL inputs are allowed on that bank? Anything else
attached to that bank that you haven't constrained the I/O type? Does it
work with LVDS inputs?
Good luck, Syms.
 
Do the p and n signals appear in your Entity declaration?

Also watch out if the instantiations are not at your very top level. I
hae seen issues in various versions of ISE if you are not at the top
level.

There shouldn't be a problem with LVPECL input on S3E providing you
have locked the p and n parts to the correct pin locations.

John Adair
Enterpoint Ltd.- Home of Drigmorn3. The Spartan-6 Industrial Control
Development Board.

On 25 Oct, 15:11, Giorgos_P <giorgos.puik...@gmail.com> wrote:
Hello,

I want to use 24 pairs of LVPECL_25 differential inputs in my design,
at a S3E500 FPGA device. During mapping, ISE gives the following
warnings and removes these inputs:

     MapLib:701 - Signal pecl_input_p<23> connected to top level port
pecl_input_p<23> has been removed.
     MapLib:701 - Signal pecl_input_n<23> connected to top level port
pecl_input_n<23> has been removed.
     ...
     MapLib:701 - Signal pecl_input_p<23> connected to top level port
pecl_input_p<0> has been removed.
     MapLib:701 - Signal pecl_input_n<23> connected to top level port
pecl_input_n<0> has been removed.

The input buffers are instantiated in VHDL like this:

     Gen1: for i in 23 downto 0 generate
        IBUFDS_inst : IBUFDS  generic map (IOSTANDARD => "LVPECL_25")
        port map (
           O => cmp_in(i),            -- Diff_p output (connect
directly to top-level port)
           I => pecl_input_p(i),      -- Diff_n output (connect
directly to top-level port)
           IB => pecl_input_n(i)      -- Buffer input
        );
     end generate Gen1 ;

and in the constraint file it is specified that:

     NET "pecl_input_p<0>"  LOC = "p57" | IOSTANDARD = LVPECL_25 ;
     NET "pecl_input_n<0>"  LOC = "p58" | IOSTANDARD = LVPECL_25 ;
     ...

The "cmp_in" output of the buffer is used and has load connected to
it, that is not removed from optimization steps. The problem seems to
be buffer-related, when I remove the buffer the inputs are not removed
by ISE. I also tried instantiating the buffer with following way,
getting the same results:

   Gen1: for i in 23 downto 0 generate
     buffer_array : IBUFDS_LVPECL_25 port map
(I=>input_p(i),IB=>input_n(i) , O=>input_int(i));
   end generate Gen1 ;

Any ideas?

Thank you in advance for your time,
George
Click to expand...
 
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