Using LUTs for array of coefficients

B

Bob

Guest
Hello again,

I have an array of 16 10 bit coefficients, and I would like to store
these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and
Altera devices by selecting various options say on Quartus, or can I
switch on any synthesis switches or do I have to change my VHDL. Any ideas
as always is greatly appreciated.

Thanks
Bob
 
Sure- they could be conveniently stored in an SRL or RAM
implementation of the LUT.

Most explicitly, you'll want to instantiate the RAMs or SRLs in VHDL.
You can infer this sort of thing but I don't really see why you would.
Simulation models can handle the simulation stuff and instantiation
makes the synthesizers job all that much easier. It's generally
easier to read the code, too.

Jake


stenasc@yahoo.com (Bob) wrote in message news:<20540d3a.0309180006.ac62b3d@posting.google.com>...
Hello again,

I have an array of 16 10 bit coefficients, and I would like to store
these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and
Altera devices by selecting various options say on Quartus, or can I
switch on any synthesis switches or do I have to change my VHDL. Any ideas
as always is greatly appreciated.

Thanks
Bob
Click to expand...
 
You can enter them through configuration (that works in Xilinx as well
as Altera).
In Xilinx FPGAs (only!) you can also treat 10 LUTs as RAM and store and
retrieve constants during operation at any time, and you can also load
the LUTs serially with the help of the SRL16 option.

Many ways...
Peter Alfke
============================
Bob wrote:
Hello again,

I have an array of 16 10 bit coefficients, and I would like to store
these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and
Altera devices by selecting various options say on Quartus, or can I
switch on any synthesis switches or do I have to change my VHDL. Any ideas
as always is greatly appreciated.

Thanks
Bob
Click to expand...
 
You'll get more consistent results by instantiating the LUTs and initializing
them with a function. The synth tools results are vendor and version
specific, especially when it so happens that one of the address inputs for a
particular bit winds up being a don't care (worst case is when the LUT bit is
constant). Also, I prefer to use SRL16's for this, as that way it is
reloadable without recompiling and reconfiguring the FPGA.

Bob wrote:

Hello again,

I have an array of 16 10 bit coefficients, and I would like to store
these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and
Altera devices by selecting various options say on Quartus, or can I
switch on any synthesis switches or do I have to change my VHDL. Any ideas
as always is greatly appreciated.

Thanks
Bob
Click to expand...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
Hello Jake/Ray

I appreciate two esteemed people like yourselves offering me your
advice.

I would rather infer than instantiate (if that doesn't sound too
rude). The reason being that I have all the VHDL written and working
in simulation and I don't have the time to redesign it. Right now I am
hoping for quick fixes to cut down on flop utilization.

The following shows a few lines on my code....

subtype data_value is std_logic_vector(15 downto 0);
type Array_A is array (0 to 15) of data_value;
signal data_a: Array_A;


Are there any directives that I could enclose the signals data_a in to
infer LUTs or SRLs instead of having to do instantiations..say for
synplify ?
I would really like to avoid instantiation if I can.

Thanks
Bob


jakespambox@yahoo.com (Jake Janovetz) wrote in message news:<d6ad3144.0309180658.4ada7252@posting.google.com>...
Sure- they could be conveniently stored in an SRL or RAM
implementation of the LUT.

Most explicitly, you'll want to instantiate the RAMs or SRLs in VHDL.
You can infer this sort of thing but I don't really see why you would.
Simulation models can handle the simulation stuff and instantiation
makes the synthesizers job all that much easier. It's generally
easier to read the code, too.

Jake


stenasc@yahoo.com (Bob) wrote in message news:<20540d3a.0309180006.ac62b3d@posting.google.com>...
Hello again,

I have an array of 16 10 bit coefficients, and I would like to store
these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and
Altera devices by selecting various options say on Quartus, or can I
switch on any synthesis switches or do I have to change my VHDL. Any ideas
as always is greatly appreciated.

Thanks
Bob
Click to expand...
 
stenasc@yahoo.com (Bob) wrote in message news:<20540d3a.0309180006.ac62b3d@posting.google.com>...
Hello again,

I have an array of 16 10 bit coefficients, and I would like to store
these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and
Altera devices by selecting various options say on Quartus, or can I
switch on any synthesis switches or do I have to change my VHDL. Any ideas
as always is greatly appreciated.

Thanks
Bob
Click to expand...
The best match in Stratix for these would be an M512 RAM (configured
as 16 bits deep x 10 wide). One RAM will handle them all. Synthesis
tools should automatically infer the RAM, and the Quartus fitter
(place and route engine) will automatically decide that this best
matches an M512 RAM and put it in one. So you shouldn't have to do
anything too special.

You could also manually instantiate an altsyncram primitive in your
HDL, but inferring really is more portable and intuitive.

Hope this helps.

Vaughn
Altera
 
I have seen very few instances where the synthesized logic did not
behave as coded. The logic turned out is nearly always 100% logically
correct, however it may not be the most efficient way of implementing
that function. Frequently with LUTs, the synthesizer will do weird
things like optimizing out unused inputs on some bits, combining
sub-terms etc. These are valid optimizations, but can make a bus wide
LUT a mess.

Tullio Grassi wrote:

On 18 Sep 2003, Bob wrote:

Hello Jake/Ray

I appreciate two esteemed people like yourselves offering me your
advice.

I would rather infer than instantiate (if that doesn't sound too
rude).
[cut]

I suspect that inferring vendor-specific embedded primitives
(like LUTs, RAM, etc) is one of the few situations where
logic simulation is not reliable, as the implementation
depends a lot on the translator.
At least I had problems with xilinx BRAM that I could
explain only in this way.
Try at least one post-PAR simulation to see if the
LUT behaves as you expect in all operating modes.

Tullio
Univ. of Maryland
Click to expand...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
On 18 Sep 2003, Bob wrote:

Hello Jake/Ray

I appreciate two esteemed people like yourselves offering me your
advice.

I would rather infer than instantiate (if that doesn't sound too
rude).
[cut]
Click to expand...

I suspect that inferring vendor-specific embedded primitives
(like LUTs, RAM, etc) is one of the few situations where
logic simulation is not reliable, as the implementation
depends a lot on the translator.
At least I had problems with xilinx BRAM that I could
explain only in this way.
Try at least one post-PAR simulation to see if the
LUT behaves as you expect in all operating modes.

Tullio
Univ. of Maryland
 
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