Using intializers in VHDL for synthesis

[valentin tihomirov]

Xilinx's "synthesis and verification guidelines" recommends omiting initial
values declaring signals telling that synthesiers ignore it. This is what I
heard about from VHDL classes. However, the following code:

if RESET = '1' then
B <= True; -- resets to False and after 100 ns resets to True
INT <= 9; -- resets to 0 and after 100 ns resets to 9
eslif CLK'event and CLK = '1' then
...

The 100 ns is used in timing netlist to simulate after-configutation reset
condition. During the reset integer registers are initialized to 0 and
boolean to false. Making external reset longer in timing test bench, the
boolean and integer go to True and 9 correspondingly. That is, XST does not
ignore the snippet above completely, there are just two different resets
internal (100 ns) and then FPGA can react to external reset. I have
discovered that the default 0 and false used during internal reset can be
changed by the initializer:
signal B: boolean := true;

Now, B resets to True during internal reset as well as during external
reset. My questions is, should we use initializers in VHDL for synthesis?