using ifdef

[James]

i need to conditionally compile a module

`ifdef SOMETHING
thiscore core();
`else
thatcore core();
`endif


It seems like it might not be safe to just `define SOMETHING in the toplevel
as there could possibly be a reset parameters directive someplace in the
project.

i have already used named parameters to pass the buswidth into the module
but i
assume i cannot do:

`ifdef BUSWIDTH=16

is there a usual (&safe) way to do this sort of thing?

thanks james

 

[Steven Sharp]

"James" <xxx@xxxx.xx> wrote in message news:<IZmdnZaBAsu3YQXcRVn-1A@comcast.com>...

It seems like it might not be safe to just `define SOMETHING in the toplevel
as there could possibly be a reset parameters directive someplace in the
project.

i have already used named parameters to pass the buswidth into the module
but i
assume i cannot do:

`ifdef BUSWIDTH=16

ifdef cannot depend on parameters, only macro definitions.

ifdef is not something that waits until you instantiate your design. It
is a preprocessor directive that is effectively performed before your
design is compiled. You can think of it as a late editing pass that
conditionally deletes some lines of your source code just before it is
compiled.

If you want to control what gets instantiated based on parameter values,
you will need to investigate Verilog-2001 conditional generates, assuming
your tools support them.