Using generate in verilog

[tsu]

I am getting compilation error in VCS with the following piece of
verilog code

module A(...)
..
..
..
..
output [(width*depth)-1:0] storage_data;
reg [depth-1 : 0] [width-1 : 0] ram_array;

genvar i;
generate
for(i=0;i<depth;i++)
assign storage_data[(((i+1)*width)-1)width*i)]=ram_array;
endgenerate
..
..
endmodule

The VCS error is pasted below

Error-[SE] Syntax error
"../vhdl/gen_ram2_jm.v", 40: token is 'assign'
assign storage_data[(((i+1)*width)-1)width*i)]=ram_array;
^
1 error

Please advice what is wrong in the above generate.

Thanks in advance,
Sujith

 

[John_H]

On Dec 5, 11:33 am, tsu <sujithredd...@gmail.com> wrote:

I am getting compilation error in VCS with the following piece of
verilog code

module A(...)
.
.
.
.
output [(width*depth)-1:0] storage_data;
reg [depth-1 : 0] [width-1 : 0] ram_array;

genvar i;
generate
for(i=0;i<depth;i++)
assign storage_data[(((i+1)*width)-1)width*i)]=ram_array;
endgenerate
.
.
endmodule

The VCS error is pasted below

Error-[SE] Syntax error
"../vhdl/gen_ram2_jm.v", 40: token is 'assign'
assign storage_data[(((i+1)*width)-1)width*i)]=ram_array;
^
1 error

Please advice what is wrong in the above generate.

Thanks in advance,
Sujith

Consider using
assign storage_data[width*i +: width] = ram_array;

Even though the assignment is simple to you and me, the variable in
both sides of the range is a problem for the base Verilog code. The
Verilog2001 construct I suggested (+ gets rid of the trouble.

- John_H

 

[Joseph H Allen]

In article <2729d477-5467-4ff6-a399-0fbc2607c3c5@s12g2000prg.googlegroups.com>,
tsu <sujithreddy.t@gmail.com> wrote:

I am getting compilation error in VCS with the following piece of
verilog code

module A(...)

Try this: I think the inside of the for needs to be a named block. The
block name ends up in the net list.

genvar i;
generate
for(i=0;i<depth;i++)
begin : foo
assign storage_data[(((i+1)*width)-1)width*i)]=ram_array;
end
endgenerate

--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0%79-77?1:0<1659?79:0>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

 

[Kevin Neilson]

Joseph H Allen wrote:

In article <2729d477-5467-4ff6-a399-0fbc2607c3c5@s12g2000prg.googlegroups.com>,
tsu <sujithreddy.t@gmail.com> wrote:
I am getting compilation error in VCS with the following piece of
verilog code

module A(...)

Try this: I think the inside of the for needs to be a named block. The
block name ends up in the net list.

genvar i;
generate
for(i=0;i<depth;i++)
begin : foo
assign storage_data[(((i+1)*width)-1)width*i)]=ram_array;
end
endgenerate

I'm not sure what the LRM says about naming generate blocks, but I have
definitely seen some synthesizers error out if the generate block isn't
named (whereas others don't). -Kevin

 

On Dec 5, 2:33 pm, tsu <sujithredd...@gmail.com> wrote:

Error-[SE] Syntax error
"../vhdl/gen_ram2_jm.v", 40: token is 'assign'
assign storage_data[(((i+1)*width)-1)width*i)]=ram_array;
^
1 error

Please advice what is wrong in the above generate

It requires a named block inside the generate-for. This provides a
scope for any declarations inside the loop. For example, if you
declared

for (i=0;i<depth;i=i+1)
integer foo;

you get multiple names foo that appear to be in the same scope, with
no distinct hierarchical path name to distinguish them. With a named
block:

for (i=0;i<depth;i=i+1)
begin:bar
integer foo;
end

you get multiple distinct scopes bar[0], bar[1], bar[2], etc. and
distinct hierarchical names bar[0].foo, bar[1].foo.

This requirement was softened in the 2005 LRM. You can leave out the
explicit named block, but you will get an implicit named block scope
with a standard compiler-generated name instead. You get such an
implicit named block scope for conditional-generates also.