using gate primitives to replace the initial and always stat

[sdaq]

can someone please explain how to use gate primitives to replace the
initial and always statements in the following clock example?

module simple_clock(clk);
output reg clk;

initial
#2 clk = 1;

always
#10 clk = ~clk;
endmodule

 

[John_H]

sdaq wrote:

can someone please explain how to use gate primitives to replace the
initial and always statements in the following clock example?

module simple_clock(clk);
output reg clk;

initial
#2 clk = 1;

always
#10 clk = ~clk;
endmodule

If you're trying to create this in hardware, it won't happen. Clocks
typically come from crystal oscillators, not from inside an FPGA or
ASIC. Silicon is not designed to give clean clocks with the sole
exception that I'm aware of being the extremely well-done silicon timing
solution called the EconOscillator from Dallas/Maxim which have
significant analog IP to accomplish the tight timing result.

If you want to change it to a NOT gate for simulation, you may be able
to apply the appropriate delays to wires to get the system to work but
there still needs to be *some* kind of initial condition applied.

So what are you trying to do?

 

[sdaq]

Thanks for your response John. From what you have said I now believe
that this was a trick question designed to teach that a clock has no
gate level implementation in Verilog.

 

It is certainly possible to build an oscillator out of an inverting
loop of gates with sufficient delay. It won't have a precise or stable
frequency, and isn't something you would do in a real design. And for
simulation purposes you would still need a mechanism to initialize it
to a known state, such as an initial block.

 

[Andy Peters]

sdaq wrote:

can someone please explain how to use gate primitives to replace the
initial and always statements in the following clock example?

module simple_clock(clk);
output reg clk;

initial
#2 clk = 1;

always
#10 clk = ~clk;
endmodule

I suppose I should point out that "initial" isn't a reset mechanism.

-a