V
Ved
Guest
I am looking forward to use FIX_STD package (jonathan.bromley).
I read the usuer manual and tried an example my self (mentioned below).
After multiplication when I see the output, the output is shown as
1110100 which when seen
in modelsim in decimal form will show -12. i.e. it shows in 2's
compliment form.
How can I see the values in fixed point form i.e. with decimal points ?
It apperas to me that there is no way to interpret that way in
Modelsim.
How can I see it than ?
-------------------------------------------------------
library work,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use work.fix_std.ALL;
entity testFixStd is
port( clock,Reset: in std_logic;
OUTcount : out integer range 0 to 2
);
end testFixStd;
architecture BEHVtestFixStd of testFixStd is
subtype SFix2p2 is SFix(FixP+1 downto FixP-2);
subtype SFix4p0 is SFix(FixP+3 downto FixP);
subtype SFix5p2 is SFix(FixP+4 downto FixP-2);
signal SF_5_2signal : SFix5p2;
begin
process(clock)
variable SF_4_0: SFix4p0 := "0110"; -- +6
variable SF_2_2: SFix2p2 := "1110"; -- -1.5
variable result: SFix5p2;
begin
Copy_V ( result,SF_2_2 * SF_4_0);
---Result is 1110100, showing -12 in decimal
SF_5_2signal <= result ;
end process;
end architecture BEHVtestFixStd;
I read the usuer manual and tried an example my self (mentioned below).
After multiplication when I see the output, the output is shown as
1110100 which when seen
in modelsim in decimal form will show -12. i.e. it shows in 2's
compliment form.
How can I see the values in fixed point form i.e. with decimal points ?
It apperas to me that there is no way to interpret that way in
Modelsim.
How can I see it than ?
-------------------------------------------------------
library work,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use work.fix_std.ALL;
entity testFixStd is
port( clock,Reset: in std_logic;
OUTcount : out integer range 0 to 2
);
end testFixStd;
architecture BEHVtestFixStd of testFixStd is
subtype SFix2p2 is SFix(FixP+1 downto FixP-2);
subtype SFix4p0 is SFix(FixP+3 downto FixP);
subtype SFix5p2 is SFix(FixP+4 downto FixP-2);
signal SF_5_2signal : SFix5p2;
begin
process(clock)
variable SF_4_0: SFix4p0 := "0110"; -- +6
variable SF_2_2: SFix2p2 := "1110"; -- -1.5
variable result: SFix5p2;
begin
Copy_V ( result,SF_2_2 * SF_4_0);
---Result is 1110100, showing -12 in decimal
SF_5_2signal <= result ;
end process;
end architecture BEHVtestFixStd;