Using file lists with Verilog

[Antal Gyori]

Hi,

Can anyone tell me the advantages and disadvantages of using one big
include file with all the verilog files in a project, versus using
`include in each file to include the files that it needs?

If using `include, how are circular/duplicate includes handled? Do
you have to use `ifdef to avoid including a file twice, something like
in C/C++?

 

[David Rogoff]

antalgyori@hotmail.com (Antal Gyori) writes:

If using `include, how are circular/duplicate includes handled? Do
you have to use `ifdef to avoid including a file twice, something like
in C/C++?

Yes, it's the same idea. It depends what's inside the include file
and where it's included. If it's global stuff, then it's mostly
`defines and `include-ed outside the module definition.

I use something like this:

////////////////////////////////////////
// file include_me.v

`ifdef READ_INCLUDE_ME
// do nothing - already been read - cleaner in v2000 with `ifndef
`else
`define adsfasdf
`define sadfaslkjdls
// etc, etc
`define READ_INCLUDE_ME
`endif
////////////////////////////////////////


If you're defining parameters, tasks, or functions, then you need to
`include from inside the module definition and define it for each
module (unless you define your tasks and stuff in one module and
reference them hierarchically).

David

 

[Petter Gustad]

antalgyori@hotmail.com (Antal Gyori) writes:

Hi,

Can anyone tell me the advantages and disadvantages of using one big
include file with all the verilog files in a project, versus using
`include in each file to include the files that it needs?

If using `include, how are circular/duplicate includes handled? Do
you have to use `ifdef to avoid including a file twice, something like
in C/C++?

For preprocessor directives (like define) I prefer not to use include
files at all. Simply make sure that the file containing the defines is
first in your file list, e.g.

verilog defines.v testbench.v dut.v -v library.v

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Petter Gustad]

Larry Doolittle <ldoolitt@recycle.lbl.gov> writes:

In article <m38yg72wyy.fsf@scimul.dolphinics.no>, Petter Gustad wrote:

For preprocessor directives (like define) I prefer not to use include
files at all. Simply make sure that the file containing the defines is
first in your file list, e.g.

verilog defines.v testbench.v dut.v -v library.v

I don't think that is expected to work according to the standard.
If you disagree, please quote chapter and verse.

I don't have the latest IEEE spec at hand, but an older version says:

"All Verilog compiler directives are preceded by the (` ) character.
This character is called accent grave. It is different from the
character ( ), which is the single quote character. The scope of
compiler directives extends from the point where it is processed,
across all files processed, to the point where another compiler
directive supersedes it or the processing completes."

I would interpet "across all files processed" as they are read by the
simulator.

Xilinx synthesizers combine all the Verilog into one file,

XST has a very crude and primitive interface where there is no way of
specifying multiple files on the command line. Earlier you had to make
a single file which included all the others (like you describe). It's
a little better in the later release where you specify a list of file,
lanugage (verilog or vhdl), and library (for vhdl).

In Synopsys DC and DC FPGA I just read in the "defines.v" file before
the design files.

where order matters:

The order matters in the command line interface case I described too.
That's why I said that you should put the defines.v file first.

I don't know what form your library takes; I've never seen a
Verilog library, and I don't have the standard with me to see
if that's something it discusses.

In this case it's simply a regular verilog file, but it will not
consider unused modules as top level blocks (no warnings and possibly
no compilation or elaboration of unused modules).

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Larry Doolittle]

In article <m38yg72wyy.fsf@scimul.dolphinics.no>, Petter Gustad wrote:

For preprocessor directives (like define) I prefer not to use include
files at all. Simply make sure that the file containing the defines is
first in your file list, e.g.

verilog defines.v testbench.v dut.v -v library.v

I don't think that is expected to work according to the standard.
If you disagree, please quote chapter and verse.

Xilinx synthesizers combine all the Verilog into one file,
where order matters:

`include defines.v
`include testbench.v
`include dut.v

I don't know what form your library takes; I've never seen a
Verilog library, and I don't have the standard with me to see
if that's something it discusses.

- Larry

 

[Petter Gustad]

Petter Gustad <newsmailcomp5@gustad.com> writes:

XST has a very crude and primitive interface where there is no way of
specifying multiple files on the command line. Earlier you had to make
a single file which included all the others (like you describe). It's
a little better in the later release where you specify a list of file,
lanugage (verilog or vhdl), and library (for vhdl).

It appears that it works to put the defines.v file first in the file
list with XST as well (at least with the more recent release):

verilog work defines.v
verilog work dut.v

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Antal Gyori]

antalgyori@hotmail.com (Antal Gyori) wrote in message news:<27418879.0405041515.120284c8@posting.google.com>...

Hi,

Can anyone tell me the advantages and disadvantages of using one big
include file with all the verilog files in a project, versus using
`include in each file to include the files that it needs?

If using `include, how are circular/duplicate includes handled? Do
you have to use `ifdef to avoid including a file twice, something like
in C/C++?

------------------------------------------------------------------------------

I am interested in your opinion on using include files vs. `include
statements for an entire design, not just for including a file with
define statements, etc, this for a large hierarchical design with at
least 3-4 levels of hierarchy.
For example, in the file declaring the alu I would import shift.v,
adder.v, other subunits. Thanks in advance for your help.