Using DLL "locked" output as a global reset signal ?

[Guy Eschemann]

I would like to use the "locked" output of a DLL to make sure that my
internal logic (ie. FSMs) doesn't start-up until a stable system clock
is available.

I'm not sure if the "locked" signal is already a synchronous one, or
if I better use a 2-stage synchronizing circuit to move it to my
system-clock domain. Anyone knows ?

Many thanks,
Guy.

 

[Austin Lesea]

Guy,

LOCKED is an output from the state machine which is clocked by CLKIN.

That makes it synchronous. It must follow (shortly) after a rising
CLKIN edge.

PSDONE is from the phase shift state machine, so that output is
synchronous to that clock. If PSCLK and CLKIN are from the same source,
then that solves that.

Austin

Guy Eschemann wrote:

I would like to use the "locked" output of a DLL to make sure that my
internal logic (ie. FSMs) doesn't start-up until a stable system clock
is available.

I'm not sure if the "locked" signal is already a synchronous one, or
if I better use a 2-stage synchronizing circuit to move it to my
system-clock domain. Anyone knows ?

Many thanks,
Guy.